Intel Arria 10 User Manual

6.15.2.1. Capability Registers
The capability registers provide high level information about the transceiver channel
and PLL configuration.
The capability registers capture a set of chosen capabilities of the PHY that cannot be
reconfigured. The following capability registers are available for the Native PHY IP
core.
Table 284. Capability Registers for the Native PHY IP Core
Address Type Name Description
0x200[7:0] RO IP Identifier Unique identifier for the Native PHY IP instance.
0x204[0] RO Status Register Enabled Indicates whether the status registers have been
enabled. 1'b1 indicates that the status registers are
enabled.
0x205[0] RO Control Register Enabled Indicates whether the control registers have been
enabled. 1'b1 indicates that the control registers are
enabled.
0x210[7:0] RO Number of Channels Shows the number of channels specified for the
Native PHY IP instance.
0x211[7:0] RO Channel Number Shows the unique channel number.
0x212[7:0] RO Duplex Shows the transceiver mode:
• 2'b00 = Unused
• 2'b01 = TX
• 2'b10 = RX
• 2'b11 = Duplex
0x213[0] RO PRBS Soft Enabled Indicates whether the PRBS soft accumulators are
enabled. 1’b1 indicates the accumulators are
enabled.
The following capability registers are available for the PLL IP cores.
Table 285. Capability Registers for the PLL IP Cores
Address Type Name Description
0x200[7:0] RO IP Identifier Unique identifier for the PLL IP instance.
0x204[0] RO Status Register Enabled Indicates if the status registers have been enabled or
not. 1'b1 indicates that the status registers have
been enabled.
0x205[0] RO Control Register Enabled Indicates if the control registers have been enabled
or not. 1'b1 indicates that the control registers have
been enabled.
0x210[7:0] RO Master CGB Enabled Indicates if the Master Clock Generation Block has
been enabled. 1'b1 indicates the master CGB is
enabled.
6.15.2.2. Control and Status Registers
Control and status registers are optional registers that memory-map some of the
status outputs from and control inputs to the Native PHY and PLL.
The following control and status registers are available for the Native PHY IP core.
6. Reconfiguration Interface and Dynamic Reconfiguration
UG-01143 | 2018.06.15
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10 Transceiver PHY User Guide
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Intel Arria 10 Specifications

General

Brand	Intel
Model	Arria 10
Category	Transceiver
Language	English