Intel Arria 10 User Manual

Related Information
• PLLs and Clock Networks on page 347
• Transceiver Basics
Online training course for transceivers.
1.2.2. PHY Layer Transceiver Components
Transceivers in Arria 10 devices support both Physical Medium Attachment (PMA) and
Physical Coding Sublayer (PCS) functions at the physical (PHY) layer.
A PMA is the transceiver's electrical interface to the physical medium. The transceiver
PMA consists of standard blocks such as:
• serializer/deserializer (SERDES)
• clock and data recovery PLL
• analog front end transmit drivers
• analog front end receive buffers
The PCS can be bypassed with a PCS Direct configuration. Both the PMA and PCS
blocks are fed by multiple clock networks driven by high performance PLLs. In PCS
Direct configuration, the data flow is through the PCS block, but all the internal PCS
blocks are bypassed. In this mode, the PCS functionality is implemented in the FPGA
fabric.
1.2.2.1. The GX Transceiver Channel
Figure 16. GX Transceiver Channel in Full Duplex Mode.
Standard PCS
PCIe Gen3 PCS
Enhanced PCSKR FEC
PCS Direct
Hard IP
(Optional)
Soft PIPE
(Optional)
FPGA Fabric
Transmitter PCS
Transmitter PMA
Serializer
Standard PCS
PCIe Gen3 PCS
Enhanced PCSKR FEC
PCS Direct
Receiver PCS
Receiver PMA
DeserializerCDR
Notes:
(1) The FPGA Fabric - PCS and PCS-PMA interface widths are configurable.
(1)
(1)
(1)
(1)
Arria 10 GX transceiver channels have three types of PCS blocks that together support
continuous data rates between 1.0 Gbps and 17.4 Gbps.
1. Arria
®
10 Transceiver PHY Overview
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
25

Intel Arria 10 Specifications

General

Brand	Intel
Model	Arria 10
Category	Transceiver
Language	English