Intel Arria 10 User Manual

7.6. Calibration Revision History
Document
Version
Changes
2018.06.15 Made the following change:
• Added a footnote: CDR and CMU PLL calibration are part of RX PMA calibration.
2017.11.06 Made the following changes:
• Updated the flow of "User Recalibration" topic.
• Updated "
— In order to trigger user re-calibration:
• Write 0x01 to offset address 0x000 [7:0], user re-calibration has to request through offset
address 0x100.
— In order to trigger DFE adaptation:
• Write 0x03 to offset address 0x000 [7:0], DFE adaptation triggering has to enable through
0x100[6].
— If you no longer need to use the internal reconfiguration bus:
• Write 0x03 to offset address 0x000 [7:0].
" in the "Reconfiguration Interface and Arbitration with PreSICE Calibration Engine" topic.
• Updated "You must also set the 0x100 [6] to 0x0 when you enable any PMA channel calibration to
ensure adaptation triggering is disabled." in "User Recalibration" topic.
• Updated "PMA Calibration Enable Register Offset Address 0x100" fto "Write 1'b0 to 0x100 [6] when
you enable any PMA channel calibration to ensure adaptation triggering request is disable." for bit 6
in "Transceiver Channel PMA Calibration Registers" table.
2016.10.31 Made the following change:
• In table "Avalon-MM Interface Arbitration Registers" the description for bit [1] is changed to
"0x1=calibration completed and 0x0=calibration not started".
2016.05.02 • Changed the "user calibration" flow.
• Changed the "power up calibration" sequence.
• Added descriptions for “Simplex calibration".
• Added a new section “Rules to Build Customized Gating Logic to Separate tx_cal_busy and
rx_cal_busy signals”.
• Updated the “Power-up Calibration Sequence for Non-PCIe Hard IP (HIP) Channels”, “Power-up
Calibration Sequence for PCIe Hard IP and non-PCIe Channels”, and “Recalibration Sequence when
the Transceiver Reference Clock or Data Rate Changes” figures.
• Changed the order of the “User Recalibration” steps in the “Recalibration After Transceiver
Reference Clock Frequency or Data Rate Change” section.
2015.12.18 Made the following changes:
• Changed the description in the "Rate Switch Flag Register" section.
• Added more description to the "User Recalibration" section.
• Added information in the "PMA Recalibration" section.
2015.11.02 Made the following changes:
• Changed the description in the "Reconfiguration Interface and Arbitration with PreSICE Calibration
Engine" section.
• Changed the description in the "Calibration Registers" section.
• Changed the "Transceiver Channel PMA Calibration Registers for Production Devices" table.
• Removed description from the "Transceiver Channel Calibration Registers" section.
• Changed values in the "Fractional PLL Calibration Registers" table.
• Changed the "PMA Capability Registers for Calibration Status" table.
• Added the "ATX PLL Capability Registers for Calibration Status" table.
• Added the "fPLL Capability Registers for Calibration Status" table.
• Added description to the "Capability Registers" section.
• Added the "Rate Switch Flag Register" section.
• Added steps to the "User Recalibration" section.
• Changed the description in the "CDR/CMU PLL Recalibration" section.
• Added steps to the "PMA Recalibration" section.
continued...
7. Calibration
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
583

Intel Arria 10 Specifications

General

Brand	Intel
Model	Arria 10
Category	Transceiver
Language	English