Intel Arria 10 User Manual

3.8. Unused/Idle Clock Line Requirements
Unused or idle transceiver clock lines can degrade if the devices are powered up to
normal operating conditions and not configured. This affects designs that configure
transceiver RX channels to use the idle clock lines at a later date by using dynamic
reconfiguration or a new device programming file. Clock lines affected are unused, or
idle RX serial clock lines. Active RX serial clock lines and non-transceiver circuits are
not impacted by this issue.
In order to prevent the performance degradation, for idle transceiver RX channels,
recompile designs with Intel Quartus Prime version 16.1 or later with the assignment
described in the link shown below. The CLKUSR pin must be assigned a 100-125 MHz
clock. For used transceiver TX and RX channels, do not assert the analog reset signals
indefinitely.
Related Information
Unused Transceiver channels Settings on page 606
For more information about unused or idle transceiver clock lines in the design. It
describes the unused or idle RX serial clock lines assignments in the qsf file.
3.9. Channel Bonding
For Arria 10 devices, two types of bonding modes are available:
• PMA bonding
• PMA and PCS bonding
Note: Channel bonding is not supported by GT channels.
Related Information
Resetting Transceiver Channels on page 416
Refer to the Timing Constraints for Bonded PCS and PMA Channels section in the
Resetting Transceiver Channels chapter for additional details.
3.9.1. PMA Bonding
PMA bonding reduces skew between PMA channels. In PMA bonding, only the PMA
portion of the transceiver datapath is skew compensated and the PCS is not skew
compensated.
In Arria 10 devices, there are two PMA bonding schemes:
• x6/xN bonding
• PLL feedback compensation bonding
In either case, the channels in the bonded group need not be placed contiguously.
3.9.1.1. x6/xN Bonding
In x6/xN bonding mode, a single transmit PLL is used to drive multiple channels.
3. PLLs and Clock Networks
UG-01143 | 2018.06.15
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Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex