Intel Arria 10 User Manual

3.12. PLLs and Clock Networks Revision History
Document
Version
Changes
2018.06.15 Made the following change:
• For fPLL IP Core, added OTN_direct, SATA_Gen3 and HDMI to the range for Protocol Mode.
2017.11.06 Made the following changes:
• Updated the "ATX PLL-to-ATX PLL Spacing Guidelines" section with GT channels information.
• Added note "Sourcing reference clock from a cascaded PLL output, global clock or core clock
network will introduce additional jitter to transmit PLL output. Refer to KDB "How do I compensate
for the jitter of PLL cascading or non-dedicated clock path for Arria 10 PLL reference clock?" for
more details."
• Added guidance for jitter compliance for data rates >10 Gbps in the following sections:
— "fPLL"
— "CMU PLL"
— "Input Reference Clock Sources"
2016.10.31 Made the following change:
• New section Unused/Idle Clock Line Requirements added.
2016.05.02 • Updated ATX PLL, fPLL and CMU PLL parameters.
• Updated ATX PLL and fPLL ports.
• Added new parameters and ports when fPLL is used in core mode.
• Provided additional details for ATX PLL and fPLL fractional mode usage in the "Delta Sigma
Modulator" section.
• Added a new section describing "ATX PLL multi-profile and embedded reconfiguration".
2016.02.11 Made the following changes:
• Updated the optimal performance placement guidelines for ATX PLL VCO frequencies.
• Updated placement recommendations for different protocols - OTU2e, OTU2, OC-192, 6G and 12G
SDI.
• Updated the "FPGA Fabric - Transceiver Interface Clocking" figure.
• Updated the maximum data rate to 25.8 Gbps.
2015.12.18 Made the following changes:
• Updated the “PLL Cascading” figure.
• Updated the "Dedicated Reference Clock Pins" in the "Input Reference Clock Sources" section.
2015.11.02 Made the following changes:
• Updated ATX PLL, CMU PLL and fPLL Configuration Options, Parameters and Settings.
• Updated ATX PLL placement in figures and examples.
• Clarified PLL to PLL cascade support.
• Created TX PLL Recommendations based on datarates.
• Updated ATX PLL, fPLL and CMU PLL Quartus settings.
• Added details and figures for the fPLL driving the fabric use cases.
• Updated PLL Feedback and Cascading Clock Network figure.
• Updated steps to implement PLL cascading.
2015.05.11 Made the following changes:
• Updated ATX PLL, CMU PLL and FPLL Configuration Options, Parameters and Settings.
• Modified Transmit PLLs Data Rate Range in Arria 10 Devices.
• Increased xN clock network channel span.
• Added ATX PLL to fPLL cascading details.
2014.12.15 Made the following changes:
• Added a note about PLL cascading support in ACDS 14.1 version of Quartus II software.
• Corrected the minimum data rate supported by ATX PLL in Table: Transmit PLLs in Arria 10 Devices.
• Corrected the error in PLL output frequency range for ATX PLL and CMU PLL IP cores.
• Corrected the PLL reference clock frequency range for ATX PLL IP core.
continued...
3. PLLs and Clock Networks
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
414

Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex