Intel Arria 10 User Manual

Document
Version
Changes
• Added a note about jitter performance in Input Reference Clock Sources section.
• Updated the Mix and Match Design Example figure to indicate that MCGB is used in the example.
• Changed the minimum data rate supported by the PLLs to 1 Gbps.
2014.08.15 Made the following changes:
• Changed the maximum data rate for GT channels to 25.8 Gbps.
• Changed figure "Arria 10 PLLs and Clock Networks" to indicate channel 0,1,3, and 5 have only the
CDR PLL.
• Updated figure "x1 Clock Lines" to indicate that the channel PLL of channel 1 and channel 4 can be
used as CMU PLL or as a CDR.
• Updated ATX PLL, fPLL, and CMU PLL section with a clarification about input reference clock
frequency stability at device power-up.
• Updated Instantiating ATX PLL, fPLL, and CMU PLL topics with new IP instantiation flow.
• Updated ATX PLL and fPLL architecture block diagrams to show global clock or core clock as an
input reference clock.
• Updated ATX PLL IP section with 14.0 A10 release changes
— Added fractional mode support.
— Added embedded debug parameters in table ATX PLL Dynamic Reconfiguration.
• Updated fPLL IP section with 14.0A10 release changes
— Removed "fPLL -Clock Switch over Parameter and Settings" table.
— Updated table "fPLL Parameter and Settings".
— Added embedded debug parameters in table "fPLL - Dynamic Reconfiguration Parameters and
Settings".
— Removed Number of auxiliary MCGB clock input ports from fPLL IP parameters.
• Added global clock or core clock as an input reference clock source.
• Added a new section for Global Clock or Core Clock as an Input Reference Clock.
• Updated figure "Input Reference Clock Sources".
• Updated Dedicated Reference Clock Pins section "Dedicated Reference Clock Pins".
— Added a connection to indicate that dedicated refclk pins can drive the reference clock network.
— Removed a wrong connection from the diagram.
• Updated xN Clock Lines section with maximum channel span limitations and added a exception for
QPI protocols.
• Added a new image in the FPGA Fabric-Transceiver Interface Clocking section.
• Added a new section for Channel Bonding describing PMA bonding, PMA and PCS bonding in detail.
• Removed xN Clock Network Data Rate Restrictions table.
• Updated chapter to indicate Arria 10 Transceivers support fPLL to fPLL, fPLL to ATX PLL, and fPLL to
CMU PLL cascading.
• Updated Using PLLs and Clock Networks section
— Changed MegaWizard references to IP Catalog and Parameter Editor.
— Updated the valid configurations for PLL IP and Native PHY IP per 14.0A10 release change.
• Removed Table "xN Clock Network Data Rate Restrictions".
• Updated the chapter to indicate Arria 10 transceivers support to fPLL to fPLL, fPLL to ATX PLL, and
fPLL to CMU PLL cascading.
2013.12.02
Initial release.
3. PLLs and Clock Networks
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
415

Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex