Intel Arria 10 User Manual

6.16.2. Using Pseudo Random Pattern Mode
You can use the Arria 10 Pseudo Random Pattern (PRP) generator and verifier in the
scrambler and descrambler to generate random data pattern and seed that the
scrambler can use. PRP mode is a test mode of the scrambler. Two seeds are available
to seed the scrambler: all 0s or two local fault-ordered sets. The seed is used in the
scrambler to produce the pattern. The r_tx_data_pat_sel is the data pattern that
the scrambler will scramble. PRP is only available when the scrambler is enabled. The
PRP verifier shares the rx_prbs_err error signal with PRBS. The error count can be
read out from the corresponding registers.
6.16.2.1. Enabling Pseudo Random Pattern Mode
You must perform a sequence of read-modify-writes to the reconfiguration interface to
enable the Pseudo Random Pattern. The read-modify-writes are required to addresses
0x082, 0x097, and 0x0AC. To enable the Pseudo Random Pattern, complete the
following steps:
1. Perform the necessary steps from steps 1 to 7 in Steps to Perform Dynamic
Reconfiguration.
2. Perform a read-modify-write to address 0x082 according to Table 295 on page
559.
3. Perform a read-modify-write to address 0x097 according to Table 295 on page
559.
4. Perform a read-modify-write to address 0x0AC according to Table 295 on page
559.
5. Perform the necessary steps from steps 9 to 12 in Steps to Perform Dynamic
Reconfiguration.
To disable the PRP verifier, write the original values back to the read-modify-write
addresses listed above.
Table 295. Register Map for Pseudo Random Pattern Mode
Reconfiguration
Address (HEX)
Reconfiguration
Bit
Attribute Name Bit Encoding Description
0x72 [7:0] r_tx_seed_a[7:0] Seed A value
bit[7:0]
0x73 [7:0] r_tx_seed_a[15:8] Seed A value
bit[15:8]
0x74 [7:0] r_tx_seed_a[23:16] Seed A value
bit[23:16]
0x75 [7:0] r_tx_seed_a[31:24] Seed A value
bit[31:24]
0x76 [7:0] r_tx_seed_a[39:32] Seed A value
bit[39:32]
0x77 [7:0] r_tx_seed_a[47:40] Seed A value
bit[47:40]
0x78 [7:0] r_tx_seed_a[55:48] Seed A value
bit[55:48]
0x79 [1:0] r_tx_seed_a[57:56] Seed A value
bit[57:56]
continued...
6. Reconfiguration Interface and Dynamic Reconfiguration
UG-01143 | 2018.06.15
Intel
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Arria
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10 Transceiver PHY User Guide
559

Intel Arria 10 Specifications

General

Brand	Intel
Model	Arria 10
Category	Transceiver
Language	English