When you perform this procedure, the Intel Quartus Prime software instantiates the
clock data recovery (CDR) PLL corresponding to each unused receiver channel. The
CDR uses CLKUSR as reference clock and is configured to run at 1 Gbps. To use
CLKUSR as reference clock, the pin must be assigned a 100- to 125 MHz clock. When
you implement these assignments, it causes a power consumption increase per
receiver channel. Please contact your local support center for details.
Related Information
Unused/Idle Clock Line Requirements on page 389
2.4.13. Unsupported Features
Native PHY should not be included in QXP.
2.5. Interlaken
Interlaken is a scalable, channelized chip-to-chip interconnect protocol.
The key advantages of Interlaken are scalability and low I/O count compared to earlier
protocols such as SPI 4.2. Other key features include flow control, low overhead
framing, and extensive integrity checking. Interlaken operates on 64-bit data words
and 3 control bits, which are striped round-robin across the lanes. The protocol
accepts packets on 256 logical channels and is expandable to accommodate up to
65,536 logical channels. Packets are split into small bursts that can optionally be
interleaved. The burst semantics include integrity checking and per logical channel
flow control.
The Interlaken interface is supported with 1 to 48 lanes running at data rates up to
12.5 Gbps per lane on Arria 10 devices. Interlaken is implemented using the Enhanced
PCS. The Enhanced PCS has demonstrated interoperability with Interlaken ASSP
vendors and third-party IP suppliers.
Arria 10 devices provide three preset variations for Interlaken in the Arria 10
Transceiver Native PHY IP Parameter Editor:
• Interlaken 10x12.5 Gbps
• Interlaken 1x6.25 Gbps
• Interlaken 6x10.3 Gbps
Depending on the line rate, the enhanced PCS can use a PMA to PCS interface width of
32, 40, or 64 bits.
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Intel
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Arria
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10 Transceiver PHY User Guide
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