Intel Arria 10 User Manual

6.12.2. Changing CTLE Settings in Manual Mode Using Direct
Reconfiguration Flow
You can use the reconfiguration interface on the Transceiver Native PHY IP core to
change the CTLE settings in manual mode.
1. Perform the necessary steps from steps 1 to 7 in Steps to Perform Dynamic
Reconfiguration.
2. Read from the CTLE feature address of the channel you want to change. For
example, to change CTLE AC gain in high gain mode, read and store the value of
address 0x167[5:1].
3. Select a valid value for the feature according to the Arria 10 register map. For
example, a valid setting for CTLE AC Gain has a bit encoding of 5’b00000.
4. Perform a read-modify-write to the address of the CTLE feature using the valid
value. For example, to change the CTLE AC gain in high gain mode, write
5’b00000 to address 0x167[5:1].
5. Perform the necessary steps from steps 9 to 12 in Steps to Perform Dynamic
Reconfiguration.
Table 275. Register Map for CTLE Settings
CTLE Feature Address Bits Values Description
One Stage Enable 0x11B [3] 1’b0- Selects Four Stage
1’b1- Selects One Stage
Selects the equalizer path as either
One Stage or Four Stage mode.
DC Gain 0x11C,
0x11A
[3:0], [7:0] 12’b000000000000
12’b111000000000
12’b111111000000
12’b111111111000
12’b111111111111
Sets the DC gain values. This
register can only be controlled when
in Four stage mode.
CTLE AC Gain One
Stage
0x166 [4:1] 4’b0000- 4’b1111 Sets the AC gain value when one
stage mode (High data rate mode) is
selected. A higher value means
higher peaking by suppressing DC
gain.
CTLE AC Gain Four
Stage
0x167 [5:1] 5’b00000 – 5’b11100 Sets the AC gain value when four
stage mode (High gain mode) is
selected.
VGA SEL 0x160 [3:1] 3’b000 – 3’b111 Sets the VGA Gain value
Related Information
• Steps to Perform Dynamic Reconfiguration on page 516
• Arria 10 PMA Architecture on page 447
6.12.3. CTLE Settings in Triggered Adaptation Mode
CTLE triggered adaptation mode should only be used for PCIe Gen3. Refer to the
section "How to enable CTLE and DFE" in Chapter Arria 10 Transceiver PHY
Architecture of Arria 10 Transceiver PHY User Guide for details on using the triggered
adaptation mode of CTLE.
User need to change the register bit settings accordingly when moving from PCIe
Gen1/2 (CTLE manual, DFE disabled) to PCIe Gen3 (CTLE triggered, DFE disabled) or
vice versa. Refer to Table 276 on page 532 for the difference in register bit settings
6. Reconfiguration Interface and Dynamic Reconfiguration
UG-01143 | 2018.06.15
Intel
®
Arria
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10 Transceiver PHY User Guide
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Intel Arria 10 Specifications

General

Brand	Intel
Model	Arria 10
Category	Transceiver
Language	English