Intel Arria 10 User Manual

Table 48. Reset Ports
Name Direction Clock Domain
(34)
Description
tx_analogreset[<n>-1:
0]
Input Asynchronous Resets the analog TX portion of the transceiver
PHY.
tx_digitalreset[<n>-1
:0]
Input Asynchronous Resets the digital TX portion of the transceiver
PHY.
rx_analogreset[<n>-1:
0]
Input Asynchronous Resets the analog RX portion of the transceiver
PHY.
rx_digitalreset[<n>-1
:0]
Input Asynchronous Resets the digital RX portion of the transceiver
PHY.
2.4.9. Enhanced PCS Ports
Figure 24. Enhanced PCS Interfaces
The labeled inputs and outputs to the PMA and PCS modules represent buses, not individual signals.
reconfig_reset
reconfig_clk
reconfig_avmm
TX Parallel Data, Control, Clocks
Enhanced PCS TX FIFO
Interlaken Frame Generator
Reconfiguration
Registers
TX Enhanced PCS
RX Enhanced PCS
Nios Hard
Calibration IP
TX PMA
Serializer
RX PMA
DeserializerCDR
tx_cal_busy
rx_cal_busy
Serial Data
Optional Ports
CDR Control
QPI
Serial Data
Clock
Generation
Block
tx_serial_clk0
(from TX PLL)
tx_analog_reset
RX Parallel Data, Control, Clocks
Enhanced PCS RX FIFO
Interlaken Frame Synchronizer
10GBASE-R BER Checker
Bitslip
Bitslip
rx_analog_reset
Clocks
PRBS
Optional Ports
Clocks
QPI
Arria 10 Transceiver Native PHY
In the following tables, the variables represent these parameters:
• <n>—The number of lanes
• <d>—The serialization factor
• <s>— The symbol size
• <p>—The number of PLLs
(34)
Although the reset ports are not synchronous to any clock domain, Intel recommends that you
synchronize the reset ports with the system clock.
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
76

Intel Arria 10 Specifications

General

Brand	Intel
Model	Arria 10
Category	Transceiver
Language	English