Intel Arria 10 User Manual

Name Direction Clock Domain Description
rx_pma_iqtxrx_clko
ut
Output Clock This port is available if you turn on Enable rx_
pma_iqtxrx_clkout port in the Transceiver Native PHY IP
core Parameter Editor. This output clock can be used to
cascade the RX PMA output clock to the input of a PLL.
rx_pma_clkslip
Output Clock When asserted, indicates that the deserializer has either
skipped one serial bit or paused the serial clock for one cycle to
achieve word alignment. As a result, the period of the parallel
clock could be extended by 1 unit interval (UI) during the clock
slip operation.
rx_pma_qpipulldn[<
n>-1:0]
Input Asynchronous This port is only used for Quick Path Interconnect (QPI)
applications.
rx_is_lockedtodat
a[<n>-1:0]
Output
rx_clkout
When asserted, indicates that the CDR PLL is locked to the
incoming data, rx_serial_data.
rx_is_lockedtoref[
<n>-1:0]
Output
rx_clkout
When asserted, indicates that the CDR PLL is locked to the
input reference clock.
rx_set_locktodata[
<n>-1:0]
Input Asynchronous This port provides manual control of the RX CDR circuitry.
rx_set_locktoref[<
n>-1:0]
Input Asynchronous This port provides manual control of the RX CDR circuitry.
rx_seriallpbken[<n
>-1:0]
Input Asynchronous This port is available if you turn on Enable rx_ seriallpbken
port in the Transceiver Native PHY IP core Parameter Editor.
The assertion of this signal enables the TX to RX serial
loopback path within the transceiver. This signal is enabled in
Duplex or Simplex mode. If enabled in Simplex mode, you
must drive the signal on both the TX and RX instances from
the same source. Otherwise the design fails compilation.
rx_prbs_done[<n>-1
:0]
Output
rx_coreclkin
or rx_clkout
When asserted, indicates the verifier has aligned and captured
consecutive PRBS patterns and the first pass through a
polynomial is complete.
rx_prbs_err[<n>-1:
0]
Output
rx_coreclkin
or rx_clkout
When asserted, indicates an error only after the
rx_prbs_done signal has been asserted. This signal gets
asserted for three parallel clock cycles for every error that
occurs. Errors can only occur once per word.
rx_prbs_err_clr[<n
>-1:0]
Input
rx_coreclkin
or rx_clkout
When asserted, clears the PRBS pattern and deasserts the
rx_prbs_done signal.
Table 47. Calibration Status Ports
Name Direction Clock Domain Description
tx_cal_busy[<n>-1:0]
Output Asynchronous When asserted, indicates that the initial TX
calibration is in progress. For both initial and
manual recalibration, this signal is asserted
during calibration and deasserts after calibration
is completed. You must hold the channel in
reset until calibration completes.
rx_cal_busy[<n>-1:0]
Output Asynchronous When asserted, indicates that the initial RX
calibration is in progress. For both initial and
manual recalibration, this signal is asserted
during calibration and deasserts after calibration
is completed.
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
75

Intel Arria 10 Specifications

General

Brand	Intel
Model	Arria 10
Category	Transceiver
Language	English