Intel Arria 10 - Implementing Protocols in Intel Arria 10 Transceivers Revision History

Simulator Simulation File Use
Synopsys VCS /simulation/synopsys/vcs/
vcs_setup.sh
Add your testbench file name to this file to pass the testbench file
to VCS using the –file option. If you specify a testbench file for
NativeLink and do not choose to simulate, NativeLink generates a
script that runs VCS.
Synopsys VCS MX /simulation/synopsys/
vcsmx/vcsmx_setup.sh
Run this script at the command line using quartus_sh–t
<script>. Any testbench you specify with NativeLink is included
in this script.
Cadence Incisive
(NCSim)
/simulation/cadence/
ncsim_setup.sh
Run this script at the command line using quartus_sh –t
<script>. Any testbench you specify with NativeLink is included in
this script.
2.11. Implementing Protocols in Intel Arria 10 Transceivers
Revision History
Document
Version
Changes
2018.06.15 Made the following changes:
• For the 1G/2.5G/5G/10G Multi-rate Ethernet status signal, added a Clock Domain column and
values for all except led_char_err.
• Changed the Gen1 PIPE PLL output frequency from 1250MHz to 2500MHz in fPLL IP Parameter Core
Settings for PIPE and ATX PLL IP Parameter Core Settings for PIPE.
• Updated Disabling/Enabling PRBS Pattern Inversion to address the hard PRBS generator and
checker pattern being inverted.
• Updated the description of 0x4C0 bit 5 Override AN Parameters Enable to refer to 0x4C3 and
changed the start address of the reserved space to 0x4D7 in 10GBASE-KR PHY Register Definitions.
• Changed the start address of the reserved space to 0x4D7 in 1G/10GbE Register Definitions.
• Added a frequency to the description of and added a footnote to the Selected CDR reference
clock frequency parameter in the "RX PMA Parameters" table.
• Added a note about bit slipping after the "Gearbox Parameters" table.
• Added a reference and a link to Clock and Reset Interfaces in the "1-Gigabit/10-Gigabit Ethernet
(GbE) PHY IP Core" section.
• Clarified the description of the Enable PCIe pipe_hclk_in and pipe_hclk_out ports parameter
in the "PCIe Ports" table.
•
Clarified the description of the pipe_hclk_out[0] port in the "Ports for Arria 10 Transceiver
Native PHY in PIPE Mode" table.
• Changed the values for the Number of fixed dfe taps parameter in the "RX PMA Parameters"
table of the Interlaken section.
• Changed the description of bit 15 of register address 0x4D0 in the "1G/10GbE Register Definitions"
table.
• Changed the description of bit 5 of register address 0x4C0 in the "1G/10GbE Register Definitions"
table.
2017.11.06 Made the following changes to the CPRI section:
• Removed a note from the "Transmitter and Receiver Latency" section.
Made the following changes to the 1G/2.5G/5G/10G Multi-rate Ethernet PHY IP Core section:
• Added the "Register Map" section.
2016.10.31 Made the following changes to the 1G/10 Gbps Ethernet PHY IP Core section:
• Added MII Interface signals to the "1G/10GbE PHY Top-Level Signals" figure.
• Added the MII section.
•
Added the tx_pcfifo_error_1g and rx_pcfifo_error_1g signals to the "Control and Status
Signals" table.
• Removed bit addresses from the 0x494 register in the "GMII PCS Registers" table.
• Changed the read/write description for the 0x495 register in the "GMII PCS Registers" table.
•
Changed the note for COPPER_DUPLEX_OPERATION in the "GMII PCS Registers" table.
continued...
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
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