2.7.8. Native PHY IP Ports for PIPE
Figure 108. Signals and Ports of Native PHY IP for PIPE
-
reconfig_reset
reconfig_clk
reconfig_avmm
tx_digitalreset
tx_datak [3:0], [1:0], or [0]
tx_parallel_data [31:0], [15:0], or [7:0]
tx_coreclkin
tx_clkout
pipe_rx_elecidle [(N-1):0]
pipe_phy_status [(N-1):0]
pipe_rate [1:0]
pipe_g3_tx_deemph [(18N-1):0]
pipe_g3_rxpresethint [(3N-1):0]
pipe_sw_done [1:0]
pipe_rx_polarity [(N-1):0]
pipe_tx_elecidle [(4N-1):0]
pipe_tx_detectrx_loopback [(N-1):0]
Gen1/Gen2/Gen3 - Black
Gen2/Gen3 - Red
Gen3 Blue
pipe_powerdown [(2N-1):0]
pipe_rx_eidleinfersel [(3N-1):0]
pipe_tx_sync_hdr [(2N-1):0]
pipe_tx_data_valid [(N-1):0]
pipe_tx_blk_start [(N-1):0]
pipe_tx_deemph [(N-1):0]
tx_bonding_clocks[(6n-1):0]
pipe_rx_data_valid [(N-1):0]
pipe_rx_blk_start [(N-1):0]
pipe_rx_sync_hdr [(2N-1):0]
tx_analogreset
rx_analogreset
rx_digitalreset
rx_datak [3:0], [1:0], or [0]
rx_parallel_data [31:0], [15:0], or [7:0]
rx_clkout
rx_coreclkin
rx_syncstatus
tx_datak [3:0], [1:0], or [0]
tx_parallel_data[31:0],[15:0],or[7:0]
tx_coreclkin
tx_clkout
unused_tx_parallel_data[118:0]
Reconfiguration
Registers
TX Standard PCS
PIPE Interface
rx_datak [3:0], [1:0], or [0]
rx_parallel_data[31:0],[15:0],or[7:0]
rx_clkout
rx_coreclkin
rx_syncstatus
unused_rx_parallel_data[118:0]
RX Standard PCS
Nios II Hard
Calibration IP
TX PMA
Serializer
RX PMA
Deserializer CDR
tx_cal_busy
rx_cal_busy
tx_serial_data
pipe_hclk_out [0]
pipe_hclk_in [0] (from TX PLL)
pipe_tx_compliance [(4N-1):0]
pipe_tx_margin [(3N-1):0]
pipe_tx_swing [(N-1):0]
pipe_rx_valid [(N-1):0]
pipe_rx_status [(3N-1):0]
pipe_sw [1:0]
rx_serial_data
rx_cdr_refclk0
rx_is_lockedtodata
rx_is_lockedtoref
Arria 10 Transceiver Native PHY
-
10
Local CGB
(for X1 Modes Only
tx_serial_data
Note: N is the number of PCIe channels
2. Implementing Protocols in Arria 10 Transceivers
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