Intel Arria 10 User Manual

In a bonded channel configuration, both the serial clock and the parallel clock are
routed from the transmitter PLL to the transmitter channel. In a non-bonded channel
configuration, only the serial clock is routed to the transmitter channel, and the
parallel clock is generated locally within the channel. To support various bonded and
non-bonded clocking configurations, four types of transmitter clock network lines are
available:
• x1 clock lines
• x6 clock lines
• xN clock lines
• GT clock lines
Related Information
Unused/Idle Clock Line Requirements on page 389
For more information about unused or idle transceiver clock lines in the design.
3.3.1. x1 Clock Lines
The x1 clock lines route the high speed serial clock output of a PLL to any channel
within a transceiver bank. The low speed parallel clock is then generated by that
particular channel's local clock generation block (CGB). Non-bonded channel
configurations use the x1 clock network.
The x1 clock lines can be driven by the ATX PLL, fPLL, or by either one of the two
channel PLLs (channel 1 and 4 when used as a CMU PLL) within a transceiver bank.
3. PLLs and Clock Networks
UG-01143 | 2018.06.15
Intel
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10 Transceiver PHY User Guide
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Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex