Intel Arria 10 - Transceiver Phase-Locked Loops

Related Information
IntelArria 10 Device Datasheet
1.2.3. Transceiver Phase-Locked Loops
Each transceiver channel in Arria 10 devices has direct access to three types of high
performance PLLs:
• Advanced Transmit (ATX) PLL
• Fractional PLL (fPLL)
• Channel PLL / Clock Multiplier Unit (CMU) PLL.
These transceiver PLLs along with the Master or Local Clock Generation Blocks (CGB)
drive the transceiver channels.
Related Information
PLLs on page 349
For more information on transceiver PLLs in Arria 10 devices.
1.2.3.1. Advanced Transmit (ATX) PLL
An advanced transmit (ATX ) PLL is a high performance PLL. It supports both integer
frequency synthesis and coarse resolution fractional frequency synthesis. The ATX PLL
is the transceiver channel’s primary transmit PLL. It can operate over the full range of
supported data rates required for high data rate applications.
Related Information
• ATX PLL on page 350
For more information on ATX PLL.
• ATX PLL IP Core on page 354
For details on implementing the ATX PLL IP.
1.2.3.2. Fractional PLL (fPLL)
A fractional PLL (fPLL) is an alternate transmit PLL used for generating lower clock
frequencies for 12.5 Gbps and lower data rate applications. fPLLs support both integer
frequency synthesis and fine resolution fractional frequency synthesis. Unlike the ATX
PLL, the fPLL can also be used to synthesize frequencies that can drive the core
through the FPGA fabric clock networks.
Related Information
• fPLL on page 359
For more information on fPLL.
• fPLL IP Core on page 362
For details on implementing the fPLL IP.
1.2.3.3. Channel PLL (CMU/CDR PLL)
A channel PLL resides locally within each transceiver channel. Its primary function is
clock and data recovery in the transceiver channel when the PLL is used in clock data
recovery (CDR) mode. The channel PLLs of channel 1 and 4 can be used as transmit
1. Arria
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10 Transceiver PHY Overview
UG-01143 | 2018.06.15
Intel
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Arria
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10 Transceiver PHY User Guide
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