Latency
The C counters can be configured to select any VCO phase and a delay of up to 128
clock cycles. The selected VCO phase can be changed dynamically.
Related Information
• Calibration on page 567
• Calibration on page 567
Details about PLL calibration
• How do I compensate for the jitter of PLL cascading or non-dedicated clock path
for Arria 10 PLL reference clock?
3.1.3.1. Instantiating the fPLL IP Core
The fPLL IP core for Arria 10 transceivers provides access to fPLLs in hardware. One
instance of the fPLL IP core represents one fPLL in the hardware.
1. Open the Quartus Prime software.
2.
Click Tools ➤ IP Catalog.
3.
In IP Catalog, under Library ➤ Transceiver PLL , select Arria 10 Transceiver
fPLL IP core and click Add.
4. In the New IP Instance dialog box, provide the IP instance name.
5. Select the Arria 10 device family.
6. Select the appropriate device and click OK.
The fPLL IP core Parameter Editor window opens.
3.1.3.2. fPLL IP Core
Table 234. fPLL IP Core Configuration Options, Parameters, and Settings
Parameters Range Description
fPLL Mode Core
Cascade Source
Transceiver
Specifies the fPLL mode of operation.
Select Core to use fPLL as a general purpose PLL to drive
the FPGA core clock network.
Select Cascade Source to connect an fPLL to another PLL
as a cascading source.
Select Transceiver to use an fPLL as a transmit PLL for the
transceiver block.
Protocol Mode Basic
PCIe* Gen1
PCIe Gen2
PCIe Gen3
SDI_cascade
OTN_cascade
SDI_direct
SATA TX
OTN_direct
SATA_Gen3
HDMI
Governs the internal setting rules for the VCO.
This parameter is not a preset. You must set all parameters
for your protocol.
Enable fractional mode On/Off Enables the fractional frequency mode.
continued...
3. PLLs and Clock Networks
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
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