Intel Arria 10 User Manual

Figure 86. Transceiver Clocking for XAUI Configuration With Phase Compensation FIFO
Enabled
When phase compensation FIFO is enabled, you can connect the core to different clocks on the Avalon-ST
interface.
RX Phase
Compensation
FIFO
TX Phase
Compensation
FIFO
Receiver Standard PCS Receiver PMA
Deserializer
CDR
Transmitter Standard PCS
Transmitter PMA
Serializer
8B/10B
Decoder
Rate Match FIFO
Deskew FIFO
Word Aligner
8B/10B Encoder
Soft PCS
XAUI PHY IP Core
xgmii_tx_clk 156.25 MHz
Parallel Clock (x6 Network)
Serial Clock
ATX PLL
Idle Rep
Idle Converter
32/64b
Avalon-ST
Adapter
MAC
36/72b
XGMII
Adapter
Master CGB
x1 Network
fPLL
REFCLK 156.25 MHz
156.25 MHz 312.5 MHz 156.25 MHz
Parallel Recovered Clock 2 (1) Parallel Recovered Clock
Serial Recovered Clock
156.25 MHz
Serial Clock (x6 Network)
Parallel Clock (x6 Network)
Parallel Recovered Clock
Serial Recovered Clock
Parallel Recovered Clock 2
Parallel Clock
Note:
1. One recovered clock drives four XAUI channels.
2.6.6.6. XAUI PHY Performance and Resource Utilization
The following table lists the typical expected device resource utilization for different
configurations using the current version of the Quartus II software targeting an Arria
10 device. The numbers of combinational ALUTs and logic registers are rounded to the
nearest 100.
Table 168. XAUI PHY Performance and Resource Utilization
Implementation Number of 3.125
Gbps Channels
Combinational ALUTs Dedicated Logic
Registers
M20K Memory Blocks
Soft XAUI 4 1700 1700 3
2.6.6.7. Parameterizing the XAUI PHY
This section contains the recommended parameter values for this protocol. Refer to
Using the Arria 10 Transceiver Native PHY IP Core for the full range of parameter
values.
Complete the following steps to configure the XAUI PHY IP core in the IP Catalog:
1. For Which device family will you be using?, select Arria 10.
2.
Click Installed IP ➤ Library ➤ Interface Protocols ➤ Ethernet ➤ XAUI PHY.
3. Use the tabs on the IP Catalog to select the options required for the protocol.
4. Refer to the following topics to learn more about the parameters:
a. General Parameters
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
221

Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex