Intel Arria 10 User Manual

3.3.3. xN Clock Lines
The xN clock lines route the transceiver clocks across multiple transceiver banks.
The master CGB drives the x6 clock lines and the x6 clock lines drive the xN clock
lines. There are two xN clock lines: xN Up and xN Down. xN Up clock lines route the
clocks to transceiver banks located above the master CGB and xN Down clock lines
route the clocks to transceiver banks located below the master CGB. The xN clock
lines can be used in both bonded and non-bonded configurations. For bonded
configurations, the low speed parallel clock output of the master CGB is used, and the
local CGB within each channel is bypassed. For non-bonded configurations, the master
CGB provides a high speed serial clock output to each channel.
3. PLLs and Clock Networks
UG-01143 | 2018.06.15
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10 Transceiver PHY User Guide
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Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex