Intel Arria 10 User Manual

Figure 225. Receiver PMA Block Diagram
Receiver
PCS
Deserializer
Parallel Data
to FPGA Core
Parallel
Data
Serial
Data
Serial Clock
Receiver PMA
CDR
Serial
Data
Receiver
Buffer
Parallel Clock
Receiver Serial
Differential Input
Data
5.1.2.1. Receiver Buffer
The receiver input buffer receives serial data from rx_serial_data and feeds the
serial data to the clock data recovery (CDR) unit and deserializer.
Figure 226. Receiver Buffer
RX
V
CM
From Serial Data
Input Pins
(rx_serial_data)
VGA
Adaptive Parametric
Tuning Engine
CTLE
DFE
RX
Termination
85Ω, 100Ω, OFF
Serial Data
The receiver buffer supports the following features:
• Programmable common mode voltage (V
CM
)
• Programmable differential On-Chip Termination (OCT)
• Signal Detector
• Continuous Time Linear Equalization (CTLE)
• Variable Gain Amplifiers (VGA)
• Adaptive Parametric Tuning Engine
• Decision Feedback Equalization (DFE)
5.1.2.1.1. Programmable Common Mode Voltage (V
CM
)
The receiver buffer has on-chip biasing circuitry to establish the required V
CM
at the
receiver input.
The Quartus Prime software automatically chooses the optimal setting for RX V
CM
.
Note:
On-chip biasing circuitry is available only if you select OCT. If you select external
termination, you must implement off-chip biasing circuitry to establish the V
CM
at the
receiver input buffer.
Manual V
CM
adjustment is not supported and is only adjusted by calibrations.
5. Arria 10 Transceiver PHY Architecture
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
451

Intel Arria 10 Specifications

General

Brand	Intel
Model	Arria 10
Category	Transceiver
Language	English