Intel Arria 10 User Manual

Bit Description
0x0: The user has control of the internal configuration bus.
0x281[1]
PMA channel rx_cal_busy active high
0x1: PMA RX calibration is running
0x0: PMA RX calibration is done
0x281[0]
PMA channel tx_cal_busy active high
0x1: PMA TX calibration is running
0x0: PMA TX calibration is done
The PMA 0x281[5:4] is used to isolate the TX and RX calibration busy status. If you
want rx_cal_busy unchanged during the TX calibration, you must set 0x281[5] to
0x0 before returning the bus to PreSICE. The channel RX is not reset due to the TX
calibration. If you want tx_cal_busy unchanged during the RX calibration, you must
set 0x281[4] to 0x0 before returning the bus to PreSICE. The channel TX is not reset
due to the RX calibration. If you accidentally write 0x00 to 0x281[5:4], tx_cal_busy
and rx_cal_busy are never activated to high in the user interface. Neither of the
0x281[1:0] registers go high either.
Table 301. ATX PLL Capability Registers for Calibration Status
Bit Description
0x280[2] PreSICE Avalon-MM interface control. This register is available to check who
controls the bus, no matter if, separate reconfig_waitrequest from the status
of AVMM arbitration with PreSICE is enabled or not.
0x1: PreSICE is controlling the internal configuration bus.
0x0: The user has control of the internal configuration bus.
0x280[1]
ATX PLL pll_cal_busy
0x1: ATX PLL calibration is running
0x0: ATX PLL calibration is done
Table 302. fPLL Capability Registers for Calibration Status
Bit Description
0x280[2] PreSICE Avalon-MM interface control
0x1: PreSICE is controlling the internal configuration bus. This register is available
to check who controls the bus, no matter if, separate reconfig_waitrequest
from the status of AVMM arbitration with PreSICE is enabled or not.
0x0: The user has control of the internal configuration bus.
0x280[1]
fPLL pll_cal_busy
0x1: fPLL calibration is running
0x0: fPLL calibration is done
7.2.6. Rate Switch Flag Register
The rate switch flag is for CDR charge pump calibration. Each SOF has CDR default
charge pump settings. After power up, these settings are loaded into the PreSICE
memory space. If you change the line rate, it may require new charge pump settings,
which are stored into the Avalon-MM reconfiguration register space. During RX PMA
calibration (including CDR), PreSICE needs to know which set of CDR charge pump
setting to use.
7. Calibration
UG-01143 | 2018.06.15
Intel
®
Arria
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10 Transceiver PHY User Guide
573

Intel Arria 10 Specifications

General

Brand	Intel
Model	Arria 10
Category	Transceiver
Language	English