Intel Arria 10 User Manual

Name Direction Clock Domain Description
receive circuitry receives all words in the reverse order. The
bit reversal circuitry operates on the output of the word
aligner.
tx_polinv[<n>-1:0]
Input Asynchronous When asserted, the TX polarity bit is inverted. Only active
when TX bit polarity inversion is enabled.
rx_polinv[<n>-1:0]
Input Asynchronous When asserted, the RX polarity bit is inverted. Only active
when RX bit polarity inversion is enabled.
rx_std_signaldetect[<n
>-1:0]
Output Asynchronous When enabled, the signal threshold detection circuitry
senses whether the signal level present at the RX input
buffer is above the signal detect threshold voltage. You can
specify the signal detect threshold using a Quartus Prime
Settings File (.qsf) assignment. This signal is required for
the PCI Express, SATA and SAS protocols.
Related Information
• ATX PLL IP Core on page 354
• CMU PLL IP Core on page 370
• fPLL IP Core on page 362
• Ports and Parameters on page 535
• Transceiver PHY Reset Controller Interfaces on page 437
• Analog Parameter Settings on page 585
2.4.11. IP Core File Locations
When you generate your Transceiver Native PHY IP, the Quartus
®
Prime software
generates the HDL files that define your instance of the IP. In addition, the Quartus
Prime software generates an example Tcl script to compile and simulate your design in
the ModelSim* simulator. It also generates simulation scripts for Synopsys* VCS,
Aldec* Active-HDL, Aldec Riviera-Pro, and Cadence* Incisive Enterprise.
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
91

Intel Arria 10 Specifications

General

Brand	Intel
Model	Arria 10
Category	Transceiver
Language	English