Intel Arria 10 User Manual

3.1.2.1. Instantiating the ATX PLL IP Core
The Arria 10 transceiver ATX PLL IP core provides access to the ATX PLLs in the
hardware. One instance of the PLL IP core represents one ATX PLL in the hardware.
1. Open the Quartus Prime software.
2.
Click Tools ➤ IP Catalog.
3.
In IP Catalog, under Library ➤ Transceiver PLL ➤ , select Arria 10
Transceiver ATX PLL and click Add.
4. In the New IP Instance dialog box, provide the IP instance name.
5. Select the Arria 10 device family.
6. Select the appropriate device and click OK.
The ATX PLL IP core Parameter Editor window opens.
3.1.2.2. ATX PLL IP Core
Table 229. ATX PLL Configuration Options, Parameters, and Settings
Parameter Range Description
Message level for rule violations Error
Warning
Specifies the messaging level to use for parameter rule
violations.
• Error—Causes all rule violations to prevent IP
generation.
• Warning—Displays all rule violations as warnings and
allows IP generation in spite of violations.
Protocol mode Basic
PCIe* Gen1
PCIe Gen2
PCIe Gen3
SDI_cascade
OTN_cascade
UPI TX
SAS TX
Governs the internal setting rules for the VCO.
This parameter is not a preset. You must set all other
parameters for your protocol.
Bandwidth Low
Medium
High
Specifies the VCO bandwidth.
Higher bandwidth reduces PLL lock time, at the expense of
decreased jitter rejection.
Number of PLL reference clocks 1 to 5 Specifies the number of input reference clocks for the ATX
PLL.
You can use this parameter for data rate reconfiguration.
Selected reference clock source 0 to 4 Specifies the initially selected reference clock input to the
ATX PLL.
Primary PLL clock output buffer GX clock output
buffer
GT clock output
buffer
Specifies which PLL output is active initially.
• If GX is selected, turn ON "Enable PLL GX clock
output port".
• If GT is selected, turn ON “Enable PLL GT clock
output port".
continued...
3. PLLs and Clock Networks
UG-01143 | 2018.06.15
Intel
®
Arria
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10 Transceiver PHY User Guide
354

Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex