Intel Arria 10 User Manual

M (integer) + K/2^32, where K is the Fractional multiply factor (K) in the ATX PLL IP
Parameter Editor
K legal values are 1 through 2^32-1 and can only be manually entered in the ATX PLL
IP Parameter Editor in Quartus Prime software.
The output frequencies can be exact when the ATX PLL is configured in fractional
mode. Due to the K value 32-bit resolution, translating to 1.63 Hz step for a 7 GHz
VCO frequency, not all desired fractional values can be achieved exactly. The lock
signal is not available, when configured in fractional mode in k-precision mode (K <
0.1 or K > 0.9).
Multiple Reconfiguration Profiles
Under the ATX PLL IP Parameter Editor Dynamic Reconfiguration tab, in the
Configuration Profiles section, multiple reconfiguration profiles can be enabled. This
allows to create, store, and analyze the parameter settings for multiple configurations
or profiles of the ATX PLL IP.
The ATX PLL IP GUI can generate configuration files (SystemVerilog, C header or MIF)
for a given configuration. With the multi reconfiguration profile options enabled, the
ATX PLL IP Parameter Editor can produce configuration files for all of the profiles
simultaneously. In addition, by enabling the reduced reconfiguration files generation,
the IP Parameter Editor produces a reduced configuration file by internally comparing
the corresponding parameter settings of all the profiles and identifying the differences.
Embedded Reconfiguration Streamer
This option enables a push-button flow to reconfigure between multiple configurations
or profiles. Here are the steps to follow:
1. Multiple reconfiguration profiles creation
• In the ATX PLL IP GUI, create configurations for each profiles using the multi-
profile feature.
2. Reconfiguration report files
• The IP GUI generates the reconfiguration report files that contain parameter
and register settings for all the selected profiles. If the reduced reconfiguration
files option is selected, the IP parameter editor compares the settings between
the profiles and generate reduced report files which only contain the
differences.
3. Select “Enable embedded reconfiguration streamer logic” in the GUI to generate
the following:
• Necessary HDL files to perform streaming.
• The individual report files for each profile, an SystemVerilog package file with
configuration data for all the profiles concatenated together which is used to
initialize the configuration ROM
4. Generate the ATX PLL IP and control the reconfiguration streamer using the AVMM
master.
Related Information
• Calibration on page 567
• How do I compensate for the jitter of PLL cascading or non-dedicated clock path
for Arria 10 PLL reference clock?
3. PLLs and Clock Networks
UG-01143 | 2018.06.15
Intel
®
Arria
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10 Transceiver PHY User Guide
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Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex