Intel Arria 10 User Manual

Parameter Range Description
threshold voltage that you specified. You can specify the signal
detect threshold using a Quartus Prime Assignment Editor or by
modifying the Quartus Settings File (.qsf)
Table 37. PCIe Ports
Parameter Range Description
Enable PCIe dynamic
datarate switch ports
On / Off
When you turn on this option, the pipe_rate, pipe_sw, and
pipe_sw_done ports are enabled. You should connect these ports
to the PLL IP core instance in multi-lane PCIe Gen2 and Gen3
configurations. The pipe_sw and pipe_sw_done ports are only
available for multi-lane bonded configurations.
Enable PCIe
pipe_hclk_in and
pipe_hclk_out ports
On / Off
When you turn on this option, the pipe_hclk_in, and
pipe_hclk_out ports are enabled. The pipe_hclk_in port
must be connected to the PLL IP core instance for the PCI Express
configurations. The pipe_hclk_out port can be left floating
when you connect tx_clkout to the MAC clock input.
Enable PCIe Gen3
analog control ports
On / Off
When you turn on this option, the pipe_g3_txdeemph and
pipe_g3_rxpresenthint ports are enabled. You can use these
ports for equalization for Gen3 configurations.
Enable PCIe electrical
idle control and status
ports
On / Off
When you turn on this option, the pipe_rx_eidleinfersel and
pipe_rx_elecidle ports are enabled. These ports are used for
PCI Express configurations.
Enable PCIe
pipe_rx_polarity port
On / Off
When you turn on this option, the pipe_rx_polarity input
control port is enabled. You can use this option to control channel
signal polarity for PCI Express configurations. When the Standard
PCS is configured for PCIe, the assertion of this signal inverts the
RX bit polarity. For other Transceiver configuration rules the
optional rx_polinv port inverts the polarity of the RX bit stream.
Related Information
• Standard PCS Ports on page 86
• Word Aligner on page 485
2.4.6. PCS Direct
Table 38. PCS Direct Datapath Parameters
Parameter Range Description
PCS Direct interface width 8, 10, 16, 20, 32, 40, 64 Specifies the data interface width between the PLD and
the transceiver PMA.
2.4.7. Dynamic Reconfiguration Parameters
Dynamic reconfiguration allows you to change the behavior of the transceiver channels
and PLLs without powering down the device.
Each transceiver channel and PLL includes an Avalon-MM slave interface for
reconfiguration. This interface provides direct access to the programmable address
space of each channel and PLL. Because each channel and PLL includes a dedicated
Avalon-MM slave interface, you can dynamically modify channels either concurrently
or sequentially. If your system does not require concurrent reconfiguration, you can
parameterize the Transceiver Native PHY IP to share a single reconfiguration interface.
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Intel
®
Arria
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10 Transceiver PHY User Guide
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Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex