Intel Arria 10 User Manual

You can use dynamic reconfiguration to change many functions and features of the
transceiver channels and PLLs. For example, you can change the reference clock input
to the TX PLL. You can also change between the Standard and Enhanced datapaths.
To enable Intel Arria 10 transceiver toolkit capability in the Native PHY IP core, you
must enable the following options:
• Enable dynamic reconfiguration
• Enable Altera Debug Master Endpoint
• Enable capability registers
• Enable control and status registers
• Enable PRBS (Pseudo Random Binary Sequence) soft accumulators
Table 39. Dynamic Reconfiguration
Parameter Value Description
Enable dynamic
reconfiguration
On/Off When you turn on this option, the dynamic reconfiguration
interface is enabled.
Share reconfiguration
interface
On/Off When you turn on this option, the Transceiver Native PHY IP
presents a single Avalon-MM slave interface for dynamic
reconfiguration for all channels. In this configuration, the upper
[n-1:10] address bits of the reconfiguration address bus specify
the channel. The channel numbers are binary encoded. Address
bits [9:0] provide the register offset address within the
reconfiguration space for a channel.
Enable Altera Debug
Master Endpoint
On/Off When you turn on this option, the Transceiver Native PHY IP
includes an embedded Altera Debug Master Endpoint (ADME) that
connects internally to the Avalon-MM slave interface for dynamic
reconfiguration. The ADME can access the reconfiguration space of
the transceiver. It can perform certain test and debug functions
via JTAG using the System Console. This option requires you to
enable the Share reconfiguration interface option for
configurations using more than one channel.
Separate
reconfig_waitrequest
from the status of
AVMM arbitration with
PreSICE
On/Off
When enabled, the reconfig_waitrequest does not indicate
the status of AVMM arbitration with PreSICE. The AVMM arbitration
status is reflected in a soft status register bit. This feature
requires that the "Enable control and status registers" feature
under "Optional Reconfiguration Logic" be enabled.
Table 40. Optional Reconfiguration Logic
Parameter Value Description
Enable capability
registers
On/Off Enables capability registers that provide high level information about the
configuration of the transceiver channel.
Set user-defined IP
identifier
User-defined Sets a user-defined numeric identifier that can be read from the
user_identifier offset when the capability registers are enabled.
Enable control and
status registers
On/Off Enables soft registers to read status signals and write control signals on the
PHY interface through the embedded debug.
Enable PRBS (Pseudo
Random Binary
Sequence) soft
accumulators
On/Off Enables soft logic for performing PRBS bit and error accumulation when the
hard PRBS generator and checker are used.
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
68

Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex