Intel Arria 10 User Manual

Table 41. Configuration Files
Parameter Value Description
Configuration file
prefix
<prefix> Here, the file prefix to use for generated configuration files is
specified. Each variant of the Transceiver Native PHY IP should use
a unique prefix for configuration files.
Generate
SystemVerilog
package file
On/Off When you turn on this option, the Transceiver Native PHY IP
generates a SystemVerilog package file,
reconfig_parameters.sv. This file contains parameters defined
with the attribute values required for reconfiguration.
Generate C header file On/Off When you turn on this option, the Transceiver Native PHY IP
generates a C header file, reconfig_parameters.h. This file
contains macros defined with the attribute values required for
reconfiguration.
Generate MIF (Memory
Initialization File)
On/Off When you turn on this option, the Transceiver Native PHY IP
generates a MIF, reconfig_parameters.mif. This file contains the
attribute values required for reconfiguration in a data format.
Include PMA analog
settings in
configuration files
On/Off When enabled, the IP allows you to configure the PMA analog
settings that are selected in the Analog PMA settings (Optional)
tab. These settings are included in your generated configuration
files.
Note: You must still specify the analog settings for your current
configuration using Quartus Prime Setting File (.qsf)
assignments in Quartus. This option does not remove the
requirement to specify Quartus Prime Setting File (.qsf)
assignments for your analog settings. Refer to the Analog
Parameter Settings chapter in the Arria 10 Transceiver PHY
User Guide for details on using the QSF assignments.
Table 42. Configuration Profiles
Parameter Value Description
Enable
multiple
reconfiguratio
n profiles
On/Off When enabled, you can use the GUI to store multiple configurations. This information is
used by Quartus to include the necessary timing arcs for all configurations during timing
driven compilation. The Native PHY generates reconfiguration files for all of the stored
profiles. The Native PHY also checks your multiple reconfiguration profiles for
consistency to ensure you can reconfigure between them. Among other things this
checks that you have exposed the same ports for each configuration.
(28)
Enable
embedded
reconfiguratio
n streamer
On/Off Enables the embedded reconfiguration streamer, which automates the dynamic
reconfiguration process between multiple predefined configuration profiles. This is
optional and increases logic utilization. The PHY includes all of the logic and data
necessary to dynamically reconfigure between pre-configured profiles.
Generate
reduced
reconfiguratio
n files
On/Off When enabled, The Native PHY generates reconfiguration report files containing only the
attributes or RAM data that are different between the multiple configured profiles. The
reconfiguration time decreases with the use of reduced .mif files.
Number of
reconfiguratio
n profiles
1-8 Specifies the number of reconfiguration profiles to support when multiple reconfiguration
profiles are enabled.
Selected
reconfiguratio
n profile
0-7 Selects which reconfiguration profile to store/load/clear/refresh, when clicking the
relevant button for the selected profile.
continued...
(28)
For more information on timing closure, refer to the Reconfiguration Interface and Dynamic
Reconfiguration chapter.
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
69

Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex