Intel Arria 10 User Manual

Port Direction Clock Domain Description
For Gen3x2,x4,x8 use the tx_bonding_clocks output from
the ATX PLL to connect to the tx_bonding_clocks input of
the Native PHY.
pcie_sw[1:0]
Input Asynchronous 2-bit rate switch control input used for PCIe protocol
implementation.
For Gen1, this port is N/A.
For Gen 2x2,x4,x8 connect the pipe_sw output from Native
PHY to this port.
For Gen3x2,x4,x8 use the pipe_sw output from Native PHY to
drive this port.
pcie_sw_done[1:0]
Output Asynchronous 2-bit rate switch status output used for PCIe protocol
implementation.
For Gen1, this port is N/A.
For Gen2x2, x4, x8 connect the pcie_sw_done output from
ATX PLL to pipe_sw_done input of Native PHY .
For Gen3x2, x4, x8 pcie_sw_done output from ATX PLL to
pipe_sw_done input of Native PHY.
Related Information
Using the Arria 10 Transceiver Native PHY IP Core on page 45
2.7.11. Preset Mappings to TX De-emphasis
Table 194. Arria 10 Preset Mappings to TX De-emphasis
Preset C
+1
C
0
C
-1
0 001111 101101 000000
1 001010 110010 000000
2 001100 110000 000000
3 001000 110100 000000
4 000000 111100 000000
5 000000 110110 000110
6 000000 110100 001000
7 001100 101010 000110
8 001000 101100 001000
9 000000 110010 001010
10 010110 100110 000000
The pipe_g3_txdeemph port is used to select the link partner’s transmitter de-
emphasis during equalization. The 18 bits specify the following coefficients:
[5:0]: C
-1
[11:6]: C
0
[17:12]: C
+1
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Intel
®
Arria
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10 Transceiver PHY User Guide
267

Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex