Intel Arria 10 User Manual

Figure 214. Reset Sequence Timing Diagram for Receiver when CDR is in Manual Lock
Mode
rx_digitalreset
rx_set_locktoref
rx_set_locktodata
rx_is_lockedtoref
rx_is_lockedtodata
rx_analogreset
rx_ready
Status Signals
Control Signals
1
2
2
4
5
6
3
1
1
1
1
2
4
4
rx_cal_busy
LTR_LTD_Manual
t
LTD_Manual
t
4.3.3. Transceiver Blocks Affected by Reset and Powerdown Signals
You must reset the digital PCS each time you reset the analog PMA or PLL. However,
you can reset the digital PCS block alone.
Table 246. Transceiver Blocks Affected by Specified Reset and Powerdown Signals
Transceiver
Block
pll_powerdown tx_analogreset tx_digitalreset rx_analogreset rx_digitalreset
CMU PLL Yes
ATX PLL Yes
fPLL Yes
CDR Yes
Receiver
Standard PCS
Yes
Receiver
Enhanced PCS
Yes
Receiver PMA Yes
Receiver PCIe
Gen3 PCS
Yes
Transmitter
Standard PCS
Yes
Transmitter
Enhanced PCS
Yes
Transmitter PMA Yes
Transmitter PCIe
Gen3 PCS
Yes
4. Resetting Transceiver Channels
UG-01143 | 2018.06.15
Intel
®
Arria
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10 Transceiver PHY User Guide
432

Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex