Related Information
• Implementing x6/xN Bonding Mode on page 404
• x6/xN Bonding on page 389
• IntelArria 10 Device Datasheet
3.3.4. GT Clock Lines
GT clock lines are dedicated clock lines available only in Arria 10 GT devices.
Each ATX PLL has two dedicated GT clock lines that connect the PLL directly to the
transceiver channels within a transceiver bank. The top ATX PLL drives channels 3 and
4, and the bottom ATX PLL drives channels 0 and 1. These connections bypass the rest
of the clock network for higher performance. These channels can be used only for
non-bonded configurations.
3. PLLs and Clock Networks
UG-01143 | 2018.06.15
Intel
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10 Transceiver PHY User Guide
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