Intel Arria 10 User Manual

Table 103. Dynamic Reconfiguration Parameters
Parameter Range
Enable dynamic reconfiguration On
Off
Share reconfiguration interface On
Off
Enable Altera Debug Master Endpoint On
Off
De-couple reconfig_waitrequest from calibration On
Off
Table 104. Configuration Files Parameters
Parameter Range
Configuration file prefix —
Generate SystemVerilog package file On
Off
Generate C header file On
Off
Generate MIF (Memory Initialization File) On
Off
Table 105. Generation Options Parameters
Parameter Range
Generate parameter documentation file On
Off
Related Information
Using the Arria 10 Transceiver Native PHY IP Core on page 45
2.6.2.4. Native PHY IP Ports for 10GBASE-R and 10GBASE-R with IEEE 1588v2
Transceiver Configurations
Figure 63. High BER
This figure shows the rx_enh_highber status signal going high when there are errors on the
rx_parallel_data output.
1122334455667788h 1122324455667788h 112233405566F788h 1122334455667788h
00h
1122334455667788h
00h
0h 1h
tx_parallel_data
tx_control
rx_parallel_data
rx_control
rx_enh_highber
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
134

Intel Arria 10 Specifications

General

Brand	Intel
Model	Arria 10
Category	Transceiver
Language	English