Intel Arria 10 User Manual

Table 98. Enhanced PCS Parameters
Parameter Range
Enhanced PCS/PMA interface width 32, 40, 64
Note: 10GBASE-R with KR-FEC allows 64 only.
FPGA fabric/Enhanced PCS interface width 66
Enable Enhanced PCS low latency mode On
Off
Enable RX/TX FIFO double-width mode Off
TX FIFO mode • Phase Compensation (10GBASE-R and 10GBASE-R
with KR FEC)
• Register or Fast register (10GBASE-R with 1588)
TX FIFO partially full threshold 11
TX FIFO partially empty threshold 2
RX FIFO mode • 10GBASE-R (10GBASE-R and 10GBASE-R with KR FEC)
• Register (10GBASE-R with 1588)
RX FIFO partially full threshold 23
RX FIFO partially empty threshold 2
Table 99. 64B/66B Encoder and Decoder Parameters
Parameter Range
Enable TX 64B/66B encoder On
Enable RX 64B/66B decoder On
Enable TX sync header error insertion On
Off
Table 100. Scrambler and Descrambler Parameters
Parameter Range
Enable TX scrambler (10GBASE-R / Interlaken) On
TX scrambler seed (10GBASE-R / Interlaken) 0x03ffffffffffffff
Enable RX descrambler (10GBASE-R / Interlaken) On
Table 101. Block Sync Parameters
Parameter Range
Enable RX block synchronizer On
Enable rx_enh_blk_lock port On
Off
Table 102. Gearbox Parameters
Parameter Range
Enable TX data polarity inversion On
Off
Enable RX data polarity inversion On
Off
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Intel
®
Arria
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10 Transceiver PHY User Guide
133

Intel Arria 10 Specifications

General

Brand	Intel
Model	Arria 10
Category	Transceiver
Language	English