Intel Arria 10 - Xaui Phy Register Interface and Register Descriptions

Signal Name Direction Description
rx_disperr signal is 2 bits wide per channel for a
total of 8 bits per XAUI link. Synchronous to
mgmt_clk.
rx_errdetect[7:0]
Output When asserted, indicates an 8B/10B code group
violation. It is asserted if the received 10-bit code
group has a code violation or disparity error. Use
rx_errdetect with the rx_disperr signal to
differentiate between a code violation error, a disparity
error, or both. The rx_errdetect signal is 2 bits
wide per channel for a total of 8 bits per XAUI link.
Synchronous to mgmt_clk.
rx_syncstatus[7:0]
Output Synchronization indication. RX synchronization is
indicated on the rx_syncstatus port of each
channel. The rx_syncstatus signal is 2 bits per
channel for a total of 8 bits per hard XAUI link. The
rx_syncstatus signal is 1 bit per channel for a total
of 4 bits per soft XAUI link. Synchronous to
mgmt_clk.
2.6.6.10. XAUI PHY Register Interface and Register Descriptions
The Avalon-MM PHY management interface provides access to the XAUI PHY IP core
PCS, PMA, and transceiver reconfiguration registers.
Table 177. Signals in the Avalon-MM PHY Management Interface
Signal Name Direction Description
phy_mgmt_clk
Input Avalon-MM clock input.
phy_mgmt_clk_reset
Input Global reset signal that resets the entire XAUI PHY. This
signal is active high and level sensitive.
phy_mgmt_addr[8:0]
Input 9-bit Avalon-MM address.
phy_mgmt_writedata[31:0]
Input 32-bit input data.
phy_mgmt_readdata[31:0]
Output 32-bit output data.
phy_mgmt_write
Input Write signal. Asserted high.
phy_mgmt_read
Input Read signal. Asserted high.
phy_mgmt_waitrequest
Output When asserted, indicates that the Avalon-MM slave
interface is unable to respond to a read or write request.
When asserted, control signals to the Avalon-MM slave
interface must remain constant.
For more information about the Avalon-MM interface, including timing diagrams, refer
to the Avalon Interface Specification.
The following table specifies the registers that you can access using the Avalon-MM
PHY management interface using word addresses and a 32-bit embedded processor. A
single address space provides access to all registers.
Note:
Writing to reserved or undefined register addresses may have undefined side effects.
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Intel
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Arria
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10 Transceiver PHY User Guide
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