Intel Arria 10 User Manual

4.4.4. Transceiver PHY Reset Controller Resource Utilization
This section describes the estimated device resource utilization for two configurations
of the transceiver PHY reset controller. The exact resource count varies by Quartus
Prime version number, as well as by optimization options.
Table 249. Reset Controller Resource Utilization
Configuration Combination ALUTs Logic Registers
Single transceiver channel approximately 50 approximately 50
Four transceiver channels, shared TX reset, separate RX resets approximately 100 approximately 150
4.5. Using a User-Coded Reset Controller
You can design your own user-coded reset controller instead of using Transceiver PHY
Reset Controller. Your user-coded reset controller must provide the following
functionality for the recommended reset sequence:
• A clock signal input for your reset logic
• Holds the transceiver channels in reset by asserting the appropriate reset control
signals
•
Checks the PLL status (for example, checks the status of pll_locked and
pll_cal_busy)
Note: You must ensure a stable reference clock is present at the PLL transmitter before
releasing pll_powerdown.
4.5.1. User-Coded Reset Controller Signals
Refer to the signals in the following figure and table for implementation of a user-
coded reset controller.
4. Resetting Transceiver Channels
UG-01143 | 2018.06.15
Intel
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10 Transceiver PHY User Guide
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Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex