Intel Arria 10 User Manual

7.5. Calibration Example
7.5.1. ATX PLL Recalibration
When you use the ATX PLL in your application, and it requires a line rate or clock
frequency change, you must recalibrate the ATX PLL after you have made the
changes.
Follow these steps to recalibrate the ATX PLL:
1. Request user access to the internal configuration bus by writing 0x2 to offset
address 0x0[7:0].
2.
Wait for reconfig_waitrequest to be deasserted (logic low) or wait until
capability register of PreSICE Avalon-MM interface control 0x280[2]=0x0.
3. To calibrate the ATX PLL, doing Read-Modify-Write 0x1 to bit[0] of address 0x100
of the ATX PLL.
4. Release the internal configuration bus to PreSICE to perform recalibration by
writing 0x1 to offset address 0x0[7:0].
5.
Periodically check the *cal_busy output signals or read the capability registers
0x280[1] to check *cal_busy status until calibration is complete.
Note: If you are recalibrating your ATX PLL and have adjacent ATX PLL used on the same
side of the device, follow the ATX PLL-to-ATX PLL spacing guideline as stated in the
"Transmit PLLs Spacing Guideline when using ATX PLLs and fPLLs" chapter.
Related Information
Transmit PLLs Spacing Guideline when using ATX PLLs and fPLLs on page 349
7.5.2. Fractional PLL Recalibration
Follow these steps to recalibrate the fPLL:
1. Request user access to the internal configuration bus by writing 0x2 to offset
address 0x0[7:0].
2.
Wait for reconfig_waitrequest to be deasserted (logic low) or wait until
capability register of PreSICE Avalon-MM interface control 0x280[2]=0x0.
3. To calibrate the fPLL, Read-Modify-Write 0x1 to bit[1] of address 0x100 of the
fPLL.
4. Release the internal configuration bus to PreSICE to perform recalibration by
writing 0x1 to offset address 0x0[7:0].
5.
Periodically check the *cal_busy output signals or read the capability registers
0x280[1] to check *cal_busy status until calibration is complete.
Note: If you are recalibrating your fPLL and have ATX PLL used on the same side of the
device, follow the fPLL-to-ATX PLL spacing guideline as stated in the "Transmit PLLs
Spacing Guideline when using ATX PLLs and fPLLs" chapter.
Related Information
Transmit PLLs Spacing Guideline when using ATX PLLs and fPLLs on page 349
7. Calibration
UG-01143 | 2018.06.15
Intel
®
Arria
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10 Transceiver PHY User Guide
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Intel Arria 10 Specifications

General

Brand	Intel
Model	Arria 10
Category	Transceiver
Language	English