Intel Arria 10 User Manual

7.5.3. CDR/CMU PLL Recalibration
CDR/CMU PLL user recalibration is integrated into the PMA RX user recalibration.
Enabling 0x100[1] PMA RX calibration recalibrates the CDR/CMU PLL.
7.5.4. PMA Recalibration
PMA calibration includes:
• PMA TX calibration
• PMA RX calibration
The PMA RX calibration includes CDR/CMU PLL calibration, offset cancellation
calibration, and V
CM
calibration. The TX PMA calibration includes TX termination, Vod,
and DCD calibration.
Follow these steps to recalibrate the PMA:
1. Request access to the internal configuration bus by writing 0x2 to offset address
0x0[7:0].
2.
Wait for reconfig_waitrequest to be deasserted (logic low), or wait until
capability register of PreSICE Avalon-MM interface control 0x281[2]=0x0.
3. Set the proper value to offset address 0x100 to enable PMA calibration. You must
also set the 0x100 [6] to 0x0 when you enable any PMA channel calibration to
ensure adaptation triggering is disabled.
4. Set the rate switch flag register for PMA RX calibration after the rate change.
• Read-Modify-Write 0x1 to offset address 0x166[7] if no rate switch.
• Read-Modify-Write 0x0 to offset address 0x166[7] if switched rate with
different CDR bandwidth setting.
5. Do Read-Modify-Write the proper value to capability register 0x281[5:4] for PMA
calibration to enable/disable tx_cal_busy or rx_cal_busy output.
•
To enable rx_cal_busy, Read-Modify-Write 0x1 to 0x281[5].
•
To disable rx_cal_busy, Read-Modify-Write 0x0 to 0x281[5].
•
To enable tx_cal_busy, Read-Modify-Write 0x1 to 0x281[4].
•
To disable tx_cal_busy, Read-Modify-Write 0x0 to 0x281[4].
6. Release the internal configuration bus to PreSICE to perform recalibration by
writing 0x1 to offset address 0x0[7:0].
7.
Periodically check the *cal_busy output signals or read the capability registers
0x281[1:0] to check *cal_busy status until calibration is complete.
Related Information
Transceiver Channel Calibration Registers on page 570
For more details about PMA recalibration
7. Calibration
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
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Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex