Intel Arria 10 - Transceiver Channel Datapath for PIPE

Table 180. Transceiver Solutions
Support Arria 10 Hard IP for PCI Express Native PHY IP Core for PCI Express
(PIPE)
Gen1, Gen2, and Gen3 data rates Yes Yes
MAC, data link, and transaction layer Yes User implementation in FPGA fabric
Transceiver interface Hard IP through PIPE 3.0 based
interface
• PIPE 2.0 for Gen1 and Gen2
• PIPE 3.0 based for Gen3 with Gen1/
Gen2 support
Related Information
• Intel PHY Interface for the PCI Express (PIPE) Architecture PCI Express
• Arria 10 Hard IP for PCI Express User Guide for the Avalon Streaming Interface
2.7.1. Transceiver Channel Datapath for PIPE
Figure 90. Transceiver Channel Datapath for PIPE Gen1/Gen2 Configurations
PIPE Interface
RX
FIFO
Byte
Deserializer
8B/10B Decoder
Rate Match FIFO
Receiver PMA
Word Aligner
Deserializer
CDR
Receiver Standard PCS
Transmitter Standard PCS
Transmitter PMA
Serializer
tx_serial_data rx_serial_data
FPGA
Fabric
TX
FIFO
Byte Serializer
8B/10B Encoder
PRBS
Generator
TX Bit Slip
PRBS
Verifier
PCI Express Hard IP
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
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