Intel Arria 10 User Manual

Table 180. Transceiver Solutions
Support Arria 10 Hard IP for PCI Express Native PHY IP Core for PCI Express
(PIPE)
Gen1, Gen2, and Gen3 data rates Yes Yes
MAC, data link, and transaction layer Yes User implementation in FPGA fabric
Transceiver interface Hard IP through PIPE 3.0 based
interface
• PIPE 2.0 for Gen1 and Gen2
• PIPE 3.0 based for Gen3 with Gen1/
Gen2 support
Related Information
• Intel PHY Interface for the PCI Express (PIPE) Architecture PCI Express
• Arria 10 Hard IP for PCI Express User Guide for the Avalon Streaming Interface
2.7.1. Transceiver Channel Datapath for PIPE
Figure 90. Transceiver Channel Datapath for PIPE Gen1/Gen2 Configurations
PIPE Interface
RX
FIFO
Byte
Deserializer
8B/10B Decoder
Rate Match FIFO
Receiver PMA
Word Aligner
Deserializer
CDR
Receiver Standard PCS
Transmitter Standard PCS
Transmitter PMA
Serializer
tx_serial_data rx_serial_data
FPGA
Fabric
TX
FIFO
Byte Serializer
8B/10B Encoder
PRBS
Generator
TX Bit Slip
PRBS
Verifier
PCI Express Hard IP
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
230

Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex