Intel Arria 10 - User Recalibration

Figure 283. Power-up Calibration Sequence for PCIe Hard IP and non-PCIe Channels
Bank 1
Bank 2
Bank ...
ATX PLL Calibration
PCIe Channels Calibration
Non-PCIe Channels Calibration
Vreg Calibration for All
Transceiver Banks and Channels
Bank 1
Bank 2
Bank ...
fPLL Calibration
Bank 1
Bank 2
Bank ...
RX PMA and TX PMA Calibration
(1)
After All ATX PLLs Calibrated
After All fPLLs Calibrated
Hard IP 0
Hard IP 1
ATX PLL Calibration
Hard IP 0
Hard IP 1
fPLL Calibration
Hard IP 0
Hard IP 1
RX PMA and TX PMA Calibration
(1)
After All ATX PLL Calibrated
After All fPLL Calibrated
(1) CDR and CMU PLL calibration are part of RX PMA calibration.
7.4. User Recalibration
User Recalibration is needed if below conditions are met:
7. Calibration
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
576