• During Device Power Up:
—
During device power up, CLKUSR is asserted and running, but the transceiver
reference clock remains deasserted until after the power up process is
complete.
—
During device power up, CLKUSR and the transceiver reference clock are
asserted and running. When the device power up process is complete, the
transceiver reference clock changes frequency. Either the transceiver reference
clock could become unstable, or your application requires a different
transceiver reference clock during normal operation, which could cause a data
rate change.
• After a dynamic reconfiguration process that triggers a data rate change:
After device power up in normal operation, you reconfigure the transceiver data
rate by changing the channel configurations or the PLLs, recalibrate the:
— ATX PLL if ATX PLL has new VCO frequency to support new data rate.
— fPLL if the fPLL has new VCO frequency to support new data rate.
Note: fPLL recalibration is not needed if the dynamic reconfiguration method
used to achieve new data rate (new VCO frequency) is done using the
fPLL L counter /1,2,4,8 division factor.
— CDU/CMU as TX PLL. You must recalibrate the RX PMA of the channel which
uses the CMU as TX PLL.
— RX PMA and TX PMA channel if the transceiver configuration changes to
support new data rates.
• Other conditions that require a user recalibration:
— Recalibrate the fPLL if the fPLL is connected as a second PLL (downstream
cascaded PLL). The downstream fPLL received the reference clock from the
upstream PLL (could be from fPLL/ CDR). Recalibrating the second fPLL is
important especially if the upstream PLL output clock (which is the
downstream fPLL's reference clock) is not present or stable during power-up
calibration.
— For ATX PLL or fPLL used to drive PLL feedback compensation bonding,
recalibrate the PLL after power up calibration.
Note: If you are recalibrating your ATX PLL or fPLL, follow the ATX PLL-to-ATX PLL or fPLL-to-
ATX PLL spacing guideline as stated in the "Transmit PLLs Spacing Guideline when
using ATX PLLs and fPLLs" chapter.
You can initiate the recalibration process by writing to the specific recalibration
registers. You must also reset the transceivers after performing user recalibration. For
example, if you perform data rate auto-negotiation that involves PLL reconfiguration,
and PLL and channel interface switching, then you must reset the transceivers.
The proper reset sequence is required after calibration. Intel recommends you use the
Transceiver PHY Reset Controller which has tx_cal_busy and rx_cal_busy inputs
and follow Intel's recommended reset sequence. You need to connect tx_cal_busy
and rx_cal_busy from the Native PHY IP core outputs to the reset controller inputs
in your design. Reset upon calibration is automatically processed when you perform
user recalibration.
7. Calibration
UG-01143 | 2018.06.15
Intel
®
Arria
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10 Transceiver PHY User Guide
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