Intel Arria 10 User Manual

Follow these steps to perform user recalibration:
1. Request internal configuration bus user access to the calibration registers by
writing 0x2 to offset address 0x0[7:0].
2.
Wait for reconfig_waitrequest to be deasserted (logic low). Or wait until
capability register of PreSICE Avalon-MM interface control =0x0. The avmm_busy
status register is 0x281[2] for PMA channel calibration and 0x280[2] for ATX PLL
and fPLL calibration.
3. Set the required calibration enable bits by doing Read-Modify-Write the proper
value to offset address 0x100. You must also set the 0x100 [6] to 0x0 when you
enable any PMA channel calibration to ensure adaptation triggering is disabled.
4. Set rate switch flag register for PMA calibration, skip this step for ATX PLL and fPLL
calibration.
• Read-Modify-Write 0x1 to offset address 0x166[7] if no CDR rate switch.
• Read-Modify-Write 0x0 to offset address 0x166[7] if switched rate with
different CDR bandwidth setting.
5. Set the proper value to capability register 0x281[5:4] for PMA calibration to
enable/disable tx_cal_busy or rx_cal_busy output.
•
To enable rx_cal_busy, Read-Modify-Write 0x1 to 0x281[5].
•
To disable rx_cal_busy, Read-Modify-Write 0x0 to 0x281[5].
•
To enable tx_cal_busy, Read-Modify-Write 0x1 to 0x281[4].
•
To disable tx_cal_busy, Read-Modify-Write 0x0 to 0x281[4].
6. Release the internal configuration bus to PreSICE to perform recalibration by
writing 0x1 to offset address 0x0[7:0]. Recalibration is in progress until the
cal_busy signals are deasserted (logic low).
7.
Periodically check the *cal_busy output signals or read the capability registers to
check *cal_busy status until calibration is complete.
Related Information
• Recommended Reset Sequence on page 418
• Implementing PLL Feedback Compensation Bonding Mode on page 405
• Implementing PLL Cascading on page 408
• Transmit PLLs Spacing Guideline when using ATX PLLs and fPLLs on page 349
7. Calibration
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
578

Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex