Intel Arria 10 User Manual

PLL Feedback Compensation Bonding Advantages over x6/xN Bonding Mode
• There is no data rate restriction. The x6 clock network used for PLL feedback
compensation bonding can run up to the maximum data rate of the device used.
• There is no channel span limitation. It is possible to bond the entire side of the
device using PLL feedback compensation.
PLL Feedback Compensation Bonding Disadvantages over x6/xN Bonding
Mode
• It uses more resources compared to x6/xN bonding. One PLL and one master CGB
are used per transceiver bank. This causes higher power consumption compared
to x6/xN bonding.
• The skew is higher compared to x6/xN bonding. The reference clock skew between
each transceiver bank is higher than the skew contributed by the xN clock network
in x6/xN bonding.
• Because the feedback clock for the PLL comes from the master CGB and not from
the PLL, the PLL feedback compensation bonding mode has a reference clock
limitation. The PLL's N-counter (reference clock divider) is bypassed resulting in
only one valid reference clock frequency for a given data rate.
• Feedback compensation bonding only supports integer mode.
Note: In order to minimize the reference clock skew for PLL feedback compensation bonding,
use a reference clock input near the center of the bonded group.
x6/xN Bonding Advantages over PLL Feedback Compensation Bonding
• x6/xN uses less resources compared to PLL feedback compensation bonding. Only
one PLL and one master CGB are required to drive all channels in the bonded
group.
• x6/xN has lower skew compared to PLL feedback compensation bonding.
Related Information
Implementing PLL Feedback Compensation Bonding Mode on page 405
3.9.2. PMA and PCS Bonding
PMA and PCS bonding reduces skew between both the PMA and PCS outputs within a
group of channels.
For PMA bonding, either x6/xN or PLL feedback compensation bonding is used. For
PCS bonding, some of the PCS control signals within the bonded group are skew
aligned using dedicated hardware inside the PCS.
3. PLLs and Clock Networks
UG-01143 | 2018.06.15
Intel
®
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10 Transceiver PHY User Guide
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Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex