Intel Arria 10 User Manual

Bit Offset Address Description
• Set this bit to 0 to request control of the internal configuration
bus by user.
• Set this bit to 1 to pass the internal configuration bus control to
PreSICE.
[1] 0x0 This bit indicates whether or not calibration is done. This is the
inverted cal_busy signal. You can write to this bit; however, if
you accidentally write 0x0 without enabling any calibration bit in
0x100, PreSICE may not set this bit to 0x1, and cal_busy remain
high. Channel reset is triggered if cal_busy is connected to the
reset controller.
• 0x1 = calibration completed.
• 0x0 = calibration not completed.
The cal_busy signal is activated two clock cycles after you
write 0x0 to this bit.
Note: During calibration when Nios is controlling the internal configuration bus, you can not
read offset address 0x0. However, you can write 0x0 to offset address 0x0[0] to
request bus access.
7.2.2. Transceiver Channel Calibration Registers
Table 297. Transceiver Channel PMA Calibration Registers
Bit PMA Calibration Enable Register Offset Address 0x100
0 Reserved
1 PMA RX calibration enable
2 Reserved
3 Reserved
4 Reserved
5 PMA TX calibration enable
6 Write 1'b0 to 0x100 [6] when you enable any PMA channel calibration to ensure adaptation
triggering request is disable.
7 Reserved
7.2.3. Fractional PLL Calibration Registers
Table 298. Fractional PLL Calibration Registers
Bit fPLL Calibration Enable Register Offset Address 0x100
0 Reserved
1 fPLL calibration enable. Set 1 to enable calibration.
(64)
The transceiver channel, ATX PLL, and fPLL use the same offset address.
7. Calibration
UG-01143 | 2018.06.15
Intel
®
Arria
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10 Transceiver PHY User Guide
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Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex