Intel Arria 10 User Manual

2.7.3. How to Connect TX PLLs for PIPE Gen1, Gen2, and Gen3 Modes
Figure 101. Use ATX PLL or fPLL for Gen1/Gen2 x1 Mode
CDR
CGB
Ch 4
CDR
CGB
Ch 3
CDR
CGB
Ch 2
CDR
CGB
Ch 1
CDR
CGB
Ch 0
CDR
CGB
Ch 5
4
4Master
CGB1
Master
CGB0
6
6
6
6
6
6
X1 Network
ATX PLL1
fPLL1
fPLL0
ATX PLL0
Path for Clocking in
Gen1/Gen2 x1 Mode
Path for Clocking in
Gen1/Gen2 x1 Mode
Notes:
1. The figure shown is just one possible combination for the PCIe Gen1/Gen2 x1 mode.
2. Gen1/Gen2 x1 mode uses the ATX PLL or fPLL.
3. Gen1/Gen2 x1 can use any channel from the given bank for which the ATX PLL or fPLL is enabled.
4. Use the pll_pcie_clk from either the ATX PLL or fPLL. This is the hclk required by the PIPE interface.
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
240

Intel Arria 10 Specifications

General

Brand	Intel
Model	Arria 10
Category	Transceiver
Language	English