Intel Arria 10 User Manual

• Reconfiguration Interface and Arbitration with PreSICE Calibration Engine on page
567
• Avalon Interface Specifications
6.2.1. Reading from the Reconfiguration Interface
Reading from the reconfiguration interface of the Transceiver Native PHY IP core or
Transceiver PLL IP core retrieves the current value at a specific address.
Figure 268. Reading from the Reconfiguration Interface
reconfig_clk
reconfig_address
reconfig_read
reconfig_waitrequest
reconfig_readdata
reconfig_write
reconfig_writedata
1
2
3
4
5
1. The master asserts reconfig_address and reconfig_read after the rising edge of reconfig_clk.
2. The slave asserts reconfig_waitrequest, stalling the transfer.
3. The master samples reconfig_waitrequest. Because reconfig_waitrequest is asserted, the cycle becomes a wait state and reconfig_address,
reconfig_read, and reconfig_write remain constant.
4. The slave presents valid reconfig_readdata and deasserts reconfig_waitrequest.
5. The master samples reconfig_waitrequest and reconfig_readdata, completing the transfer.
119h
Valid readdata
After the reconfig_read signal is asserted, the reconfig_waitrequest signal
asserts for a few reconfig_clock cycles, then deasserts. This deassertion indicates
the reconfig_readdata bus contains valid data.
Note: You must check for the internal configuration bus arbitration before performing
reconfiguration. Refer to the Arbitration section for more details about requesting
access to and returning control of the internal configuration bus from PreSICE.
Related Information
Arbitration on page 512
6.2.2. Writing to the Reconfiguration Interface
Writing to the reconfiguration interface of the Transceiver Native PHY IP core or TX PLL
IP core changes the data value at a specific address. All writes to the reconfiguration
interface must be read-modify-writes, because two or more features may share the
same reconfiguration address. When two or more features share the same
reconfiguration address, one feature's data bits are interleaved with another feature's
data bits.
6. Reconfiguration Interface and Dynamic Reconfiguration
UG-01143 | 2018.06.15
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Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex