High data rate mode is enabled by default for data rates up to 25.8 Gbps. In high data
rate mode, there is only one CTLE stage and 16 possible AC gain settings. Higher gain
setting results in larger AC gain. The default value is set to
RADP_CTLE_EQZ_1S_SEL_3 i.e. CTLE AC Gain Setting 3. This QSF assignment only
takes effect when one stage CTLE is enabled. If configured in four stage mode, it has
no effect on CTLE gain value.
For datarate > 17.4 Gbps, default value is RADP_CTLE_EQZ_1S_SEL_13.
For datarate ≤ 17.4 Gbps, default value is RADP_CTLE_EQZ_1S_SEL_3.
Table 312. Available Options
Value Description
RADP_CTLE_EQZ_1S_SEL_<0 to 15> CTLE AC Gain Setting < 0 to 15>
Assign To
RX serial data pin.
Syntax
set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_EQZ_1S_SEL
<value> -to <rx_serial_data pin name>
8.5.2. VGA Settings
8.5.2.1. XCVR_A10_RX_ADP_VGA_SEL
Pin planner or Assignment Editor Name
Receiver Variable Gain Amplifier Voltage Swing Select
Description
The variable gain amplifier (VGA) amplifies the signal amplitude and ensures a
constant voltage swing before the data is fed to the CDR for sampling. This
assignment controls the VGA output voltage swing when adaptation mode of VGA is
set to manual. The default value is set to RADP_VGA_SEL_4 for VGA Output Voltage
Swing Setting 4.
Default values for VGA if VGA are not set exclusively.
For PCIe Gen1 & Gen2: default value is RADP_VGA_SEL_4.
For PCIe Gen3: default value is RADP_VGA_SEL_4.
For datarate > 17.4 Gbps, default value is RADP_VGA_SEL_4.
For RX_LINK = LR and CTLE mode = NON_S1_MODE: default value is
RADP_VGA_SEL_4.
For RX_LINK = LR and CTLE mode = S1_MODE and datarate <= 4.5Gbps: default
value is RADP_VGA_SEL_4.
8. Analog Parameter Settings
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
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