2.8.1. Transceiver Channel Datapath and Clocking for CPRI
Figure 115. Transceiver Channel Datapath and Clocking for CPRI
RX
FIFO
Byte
Deserializer
8B/10B Decoder
Rate Match FIFO
Receiver PMA
Word Aligner
Deserializer
CDR
Receiver Standard PCS
Transmitter Standard PCS
Transmitter PMA
Serializer
tx_serial_data
rx_serial_data
FPGA
Fabric
TX
FIFO
Byte Serializer
8B/10B Encoder
PRBS
Generator
TX Bit Slip
/2, /4
/2, /4
Parallel Clock
Serial Clock
Parallel and Serial Clock
Parallel and Serial Clock
Clock Divider
rx_pma_div_clkout
Serial Clock
Clock Generation Block (CGB)
ATX PLL
CMU PLL
fPLL
tx_coreclkin
rx_coreclkin
rx_clkout or
tx_clkout
Parallel Clock
(Recovered)
Parallel Clock
(From Clock
Divider)
tx_clkout
tx_clkout
tx_clkout
rx_clkout
PRBS
Verifier
tx_pma_div_clkout
40
40
245 MHz
245 MHz
32
32
245 MHz
245 MHz
Table 200. Channel Width Options for Supported Serial Data Rates
Serial Data
Rate
(Mbps)
Channel Width (FPGA-PCS Fabric)
8/10 Bit Width 16/20 Bit Width
8-Bit 16-Bit 16-Bit 32-Bit
614.4
(45)
Yes Yes N/A N/A
1228.8 Yes Yes Yes Yes
2457.6 Yes Yes Yes Yes
3072 Yes Yes Yes Yes
4915.2 N/A N/A Yes Yes
6144 N/A N/A Yes Yes
9830.4 N/A N/A N/A Yes
Table 201. Interface Width Options for 10.1376 Gbps and 12.16512 Gbps Data Rates
Serial Data Rate
(Mbps)
Interface Width
FPGA fabric - Enhanced PCS (bit) Enhanced PCS - PMA (bit)
10137.6 66 32, 40, 64
12165.12 66 40, 64
(45)
Over-sampling is required to implement 614.4Mbps
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
280