Intel Arria 10 User Manual

Recommendations:
Intel recommends that you not reset the PLL and channels (TX and RX) when using
the PIPE mode of Native PHY. This is to avoid resetting the Auto Speed Negotiation
(ASN) block in the PCS.
Related Information
• PLLs on page 349
For information about PLL architecture and implementation details.
• Arria 10 Standard PCS Architecture on page 479
• Resetting Transceiver Channels on page 416
For information about the Reset controller and implementation details.
2.7.5. Native PHY IP Parameter Settings for PIPE
Table 184. Parameters for Arria 10 Native PHY IP in PIPE Gen1, Gen2, Gen3 Modes
This section contains the recommended parameter values for this protocol. Refer to Using the Arria 10
Transceiver Native PHY IP Core for the full range of parameter values.
Gen1 PIPE Gen2 PIPE Gen3 PIPE
Parameter
Message level for rule violations Error Error Error
Common PMA Options
VCCR_GXB and VCCT_GXB
supply voltage for the
Transceiver
Gen1: 1_1V, 1_0V, 0_9V Gen2: 1_1V, 1_0V, 0_9V Gen3: 1_1V, 1_0V, 0_9V
Transceiver link type Gen1: sr,lr Gen2: sr,lr Gen3: sr,lr
Datapath Options
Transceiver configuration rules Gen1 PIPE Gen2 PIPE Gen3 PIPE
PMA configuration rules Basic Basic Basic
Transceiver mode TX / RX Duplex TX / RX Duplex TX / RX Duplex
Number of data channels
Gen1 x1: 1 channel
Gen1 x2: 2 channels
Gen1 x4: 4 channels
Gen1 x8: 8 channels
Gen2 x1: 1 channel
Gen2 x2: 2 channels
Gen2 x4: 4 channels
Gen2 x8: 8 channels
Gen3 x1: 1 channel
Gen3 x2: 2 channels
Gen3 x4: 4 channels
Gen3 x8: 8 channels
Data rate 2.5 Gbps 5 Gbps 5 Gbps
(39)
Enable datapath and interface
reconfiguration
Optional Optional Optional
Enable simplified data interface Optional
(40)
Optional
(40)
Optional
(40)
Provide separate interface for
each channel
Optional Optional Optional
(39)
The PIPE is configured in Gen1/Gen2 during Power Up. Gen3 PCS is configured for 8 Gbps.
(40)
Refer to Table 191 on page 263 for bit settings when simplified data interface is enabled.
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Intel
®
Arria
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10 Transceiver PHY User Guide
248

Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex