Intel Arria 10 User Manual

Table 185. Parameters for Arria 10 Native PHY IP in PIPE Gen1, Gen2, Gen3 Modes - TX
PMA
This section contains the recommended parameter values for this protocol. Refer to Using the Arria 10
Transceiver Native PHY IP Core for the full range of parameter values.
Gen1 PIPE Gen2 PIPE Gen3 PIPE
TX Bonding Options
TX channel bonding mode
Nonbonded (x1)
PMA & PCS Bonding
Nonbonded (x1)
PMA & PCS Bonding
Nonbonded (x1)
PMA & PCS Bonding
PCS TX channel bonding master Auto
(41)
Auto
(41)
Auto
(41)
Default PCS TX channel bonding master
Gen1 x1: 0
Gen1 x2: 1
Gen1 x4: 2
Gen1 x8: 4
Gen1 x1: 0
Gen1 x2: 1
Gen1 x4: 2
Gen1 x8: 4
Gen1 x1: 0
Gen1 x2: 1
Gen1 x4: 2
Gen1 x8: 4
TX PLL Options
TX local clock division factor 1 1 1
Number of TX PLL clock inputs per
channel
1 1
Gen3 x1: 2
All other modes: 1
Initial TX PLL clock input selection
0 0
Gen1 / Gen2 clock
connection should be
used for Initial clock
input selection in
Gen3x1
All other modes: 0
TX PMA Optional Ports
Enable tx_analog_reset_ack port
Optional Optional Optional
Enable tx_pma_clkout port
Optional Optional Optional
Enable tx_pma_div_clkout port
Optional Optional Optional
tx_pma_div_clkout division factor
Optional Optional Optional
Enable tx_pma_elecidle port
Off Off Off
Enable tx_pma_qpipullup port (QPI)
Off Off Off
Enable tx_pma_qpipulldn port (QPI)
Off Off Off
Enable tx_pma_txdetectrx port (QPI)
Off Off Off
Enable tx_pma_rxfound port (QPI)
Off Off Off
Enable rx_seriallpbken port
Off Off Off
(41)
Setting this parameter is placement-dependent. In AUTO mode, the Native PHY IP Parameter
Editor selects the middle-most channel of the configuration as the default PCS TX channel
bonding master. You must ensure that this selected channel is physically placed as Ch1 or Ch4
of the transceiver bank. Else, use the manual selection for the PCS TX channel bonding master
to select a channel that can be physically placed as Ch1 or Ch4 of the transceiver bank. Refer
to section How to place channels for PIPE configurations for more details.
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Intel
®
Arria
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10 Transceiver PHY User Guide
249

Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex