Intel Arria 10 User Manual

5.3.1.3.6. 8B/10B Encoder Byte Reversal Feature
Figure 258. 8B/10B Encoder Byte Reversal Feature
Byte Reversal Mode
(8B/10B Encoder)
A
A
B
B
8 15 0 7 0 7 8 15
Output
Data
Input
Data
The byte reversal feature is available only when the PCS-PMA interface width is 16 bits
or 20 bits. Byte reversal is performed at the output of the 8B/10B Encoder and is
available even when the 8B/10B Encoder is disabled. This feature swaps the LSByte
with the MSByte. For example, when the PCS-PMA interface width is 16-bits, [7:0] bits
(LSByte) gets swapped with [15:8] bits (MSByte).
5.3.1.4. Polarity Inversion Feature
The polarity inversion feature is used in situations where the positive and the negative
signals of a serial differential link are erroneously swapped during board layout. You
can control this feature through tx_polinv port, by enabling the Enable TX
Polarity Inversion option under the Standard PCS tab of the Native PHY IP Core. The
polarity inversion feature inverts the value of each bit of the input data. For example,
if the input data is 00101001, then the data gets changed to 11010110 after polarity
inversion.
5.3.1.5. Pseudo-Random Binary Sequence (PRBS) Generator
Note: Refer to the PRBS Generator section in the Enhanced PCS Architecture chapter.
Related Information
Arria 10 Enhanced PCS Architecture on page 461
5.3.1.6. TX Bit Slip
The TX bit slip allows the word boundary to be controlled by
tx_std_bitslipboundarysel. The TX bit slip feature is used in applications, such
as CPRI, which has a data rate greater than 6 Gbps. The maximum number of the
supported bit slips is PCS data width-1 and the slip direction is from MSB to LSB and
from current to previous word.
5.3.2. Receiver Datapath
5.3.2.1. Word Aligner
The word aligner receives the serial data from the PMA and realigns the serial data to
have the correct word boundary according to the word alignment pattern configured.
This word alignment pattern can be 7, 8, 10, 16, 20, 32 and 40 bits in length.
5. Arria 10 Transceiver PHY Architecture
UG-01143 | 2018.06.15
Intel
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Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex