Intel Arria 10 User Manual

Note: Intel recommends transmitting Preset P8 coefficients for Arria 10 receiver to recover
data successfully.
2.7.12. How to Place Channels for PIPE Configurations
Instead of the fitter or software model, the hardware dictates all the placement
restrictions. The restrictions are listed below:
• The channels must be contiguous for bonded designs.
• The master CGB is the only way to access x6 lines and must be used in bonded
designs. The local CGB cannot be used to route clock signals to slave channels
because the local CGB does not have access to x6 lines.
• When implementing a Gen3-capable PIPE configuration in a -2 or -3 core speed
grade, you cannot place the Logical PCS Master Channel in a location adjacent to
the Hard IP (HIP).
• Non PCIe-Channels that are placed next to active banks with PIPE interfaces that
are Gen3 capable have the following restrictions
— When VCCR_GXB and VCCT_GXB are set to 1.03 V or 1.12 V, the maximum
data rate supported for the non-PCIe channels in those banks is 12.5 Gbps for
chip-to-chip applications. These channels cannot be used to drive backplanes
or for GT rates.
— When VCCR_GXB and VCCT_GXB are set to 0.95 V, the non-PCIe channels in
those banks cannot be used.
For channel placement guidelines when using Arria 10 Hard IP for PCIe, refer to the
PCIe User Guide.
For ATX PLL placement restrictions, refer to the section "Transmit PLL
Recommendations Based on Data Rates" of PLLs and Clock Networks chapter.
Related Information
• Arria 10 Avalon-MM Interface for PCIe Solutions User Guide
• PLLs and Clock Networks on page 347
2.7.12.1. Master Channel in Bonded Configurations
For PCIe, both the PMA and PCS must be bonded. There is no need to specify the PMA
Master Channel because of the separate Master CGB in the hardware. However, you
must specify the PCS Master Channel through the Native PHY. You can choose any one
of the data channels (part of the bonded group) as the logical PCS Master Channel.
Note: Whichever channel you pick as the PCS master, the fitter selects the physical CH1 or
CH4 of a transceiver bank as the master channel. This is because the ASN and Master
CGB connectivity only exists in the hardware of these two channels of the transceiver
bank.
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Intel
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10 Transceiver PHY User Guide
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Intel Arria 10 Specifications

General

Brand	Intel
Model	Arria 10
Category	Transceiver
Language	English