Intel Arria 10 User Manual

Table 195. Logical PCS Master Channel for PIPE Configuration
PIPE Configuration Logical PCS Master Channel # (default)
x1 0
(44)
x2 1
(44)
x4 2
(44)
x8 4
(44)
The following figures show the default configurations:
Figure 109. x2 Configuration
CH5
CH4
CH3
CH2
CH1
CH0
CH5
CH4
CH3
CH2
CH1
CH0
Master CH
Data CH
fPLL
ATX
PLL
Master
CGB
fPLL
ATX
PLL
fPLL
ATX
PLL
fPLL
ATX
PLL
Master
CGB
Logical
Channel
Physical
Channel
0
1
Transceiver bank
Transceiver bank
Master
CGB
Master
CGB
Note: The physical channel 0 aligns with logical channel 0. The logical PCS Master Channel 1
is specified as Physical Channel 1.
(44)
Ensure that the Logical PCS Master Channel aligns with Physical Channel 1 or 4 in a given
transceiver bank.
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Intel
®
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10 Transceiver PHY User Guide
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Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex